Pixel circuit and driving method thereof, and display panel and driving method thereof
A drive method for a display panel, wherein the display panel includes a plurality of current data lines, a plurality of time-length data lines, a first current selection signal line, a second current selection signal line, a first time-length selection signal line and a second time-length selection signal line, at least one current data line is connected with the first current selection signal line or the second current selection signal line, and at least one time-length data line is connected with the first time-length selection signal line or the second time-length selection signal line; the method includes: providing a valid level signal to the first time-length selection signal line, the second time-length selection signal line, the first current selection signal line and the second current selection signal line.
1. A drive method for a display panel, wherein:
the display panel comprises: pixel circuits arranged in array, a plurality of current data lines, a plurality of time-length data lines, a first current selection signal line, a second current selection signal line, a first time-length selection signal line and a second time-length selection signal line;
the pixel circuits are respectively connected with the current data lines and the time-length data lines, at least one current data line is connected with the first current selection signal line or the second current selection signal line, two adjacent current data lines are connected with different current selection signal lines, at least one time-length data line is connected with the first time-length selection signal line or the second time-length selection signal line, and two adjacent time-length data lines are connected with different time-length selection signal lines;
the method comprises: providing a valid level signal to the first time-length selection signal line, the second time-length selection signal line, the first current selection signal line and the second current selection signal line; and
time for at least two signal lines of the first time-length selection signal line, the second time-length selection signal line, the first current selection signal line and the second current selection signal line to receive the valid level signal is not overlapped;
wherein:
the display panel further comprises: a reset signal line, a scanning signal line, and a light-emitting signal line, the pixel circuits are respectively connected with the reset signal line, the scanning signal line and the light-emitting signal line;
the method further comprises: providing a valid level signal to the reset signal line, the scanning signal line and the light-emitting signal line; and
time for at least two signal lines of the reset signal line, the scanning signal line and the light-emitting signal line connected to a same pixel circuit to receive the valid level signal is not overlapped;
wherein: the time for the reset signal line connected to a (m+1) th row of pixel circuits to receive the valid level signal is within the time for the light-emitting signal line connected to a m th row of pixel circuits to receive the valid level signal, and 1≤m≤M and M is a total number of rows of the pixel circuits.
2. The method according to claim 1 , wherein the time for the first time-length selection signal line to receive the valid level signal is within the time for the reset signal line connected to at least one row of pixel circuits to receive the valid level signal.
3. The method according to claim 2 , wherein the time for the first time-length selection signal line to receive the valid level signal and the time for the second time-length selection signal line to receive the valid level signal are not overlapped, and a sum of a time length for the first time-length selection signal line to receive the valid level signal and a time length for the second time-length selection signal line to receive the valid level signal is less than a time length for the reset signal line connected to at least one row of pixel circuits to receive the valid level signal.
4. The method according to claim 1 , wherein the time for the second time-length selection signal line to receive the valid level signal is within the time for the reset signal line connected to at least one row of pixel circuits to receive the valid level signal.
5. The method according to claim 4 , wherein the time for the first time-length selection signal line to receive the valid level signal and the time for the second time-length selection signal line to receive the valid level signal are not overlapped, and a sum of a time length for the first time-length selection signal line to receive the valid level signal and a time length for the second time-length selection signal line to receive the valid level signal is less than a time length for the reset signal line connected to at least one row of pixel circuits to receive the valid level signal.
6. The method according to claim 1 , wherein the time for the first current selection signal line to receive the valid level signal is within the time for the scanning signal line connected to at least one row of pixel circuits to receive the valid level signal.
7. The method according to claim 6 , wherein the time for the first current selection signal line to receive the valid level signal and the time for the second current selection signal line to receive the valid level signal are not overlapped, and a sum of a time length for the first current selection signal line to receive the valid level signal and a time length for the second current selection signal line to receive the valid level signal is less than a time length for the scanning signal line connected to at least one row of pixel circuits to receive the valid level signal.
8. The method according to claim 1 , wherein the time for the second current selection signal line to receive the valid level signal is within the time for the scanning signal line connected to at least one row of pixel circuits to receive the valid level signal.
9. The method according to claim 8 , wherein the time for the first current selection signal line to receive the valid level signal and the time for the second current selection signal line to receive the valid level signal are not overlapped, and a sum of a time length for the first current selection signal line to receive the valid level signal and a time length for the second current selection signal line to receive the valid level signal is less than a time length for the scanning signal line connected to at least one row of pixel circuits to receive the valid level signal.
10. The method according to claim 1 , wherein:
the display panel further comprises: 4M control signal lines, wherein the m th row of pixel circuits are connected with a (4m−3) th control signal line, a (4m−2) th control signal line, a (4m−1) th control signal line and a (4m) th control signal line, respectively; and
the method further comprises: providing a valid level signal to the control signal lines; and
in a case that the m th row of pixel units are used for display, time for the (4m−3) th control signal line to receive the valid level signal, time for the (4m−2) th control signal line to receive the valid level signal, time for the (4m−1) th control signal line to receive the valid level signal and time for the (4m) th control signal line to receive the valid level signal are within the time for the reset signal line connected to the m th row of pixel circuits to receive the valid level signal, and the time for the (4m−3) th control signal line to receive the valid level signal, the time for the (4m−2) th control signal line to receive the valid level signal, the time for the (4m−1) th control signal line to receive the valid level signal and the time for the (4m) th control signal line to receive the valid level signal are not overlapped.
11. The method according to claim 10 , wherein the pixel circuits in odd columns of the m th row are electrically connected to the (4m−3) th control signal line and the (4m−2) th control signal line respectively, the pixel circuits in even columns of the m th row are electrically connected to the (4m−1) th control signal line and the (4m) th control signal line respectively, the time-length data lines connected to the pixel circuits in odd columns are connected to the first time-length selection signal line, and in a case that the time-length data lines connected to the pixel circuits in even columns are connected to the second time-length selection signal line, the time for the (4m−3) th control signal line to receive the valid level signal and the time for the (4m−2) th control signal line to receive the valid level signal are within the time for the first time-length selection signal line to receive the valid level signal, and the time for the (4m−1) th control signal line to receive the valid level signal and the time for the (4m) th control signal line to receive the valid level signal are within the time for the second time-length selection signal line to receive the valid level signal.
12. The method according to claim 11 , wherein:
a sum of a time length for the (4m−3) th control signal line to receive the valid level signal and a time length for the (4m−2) th control signal line to receive the valid level signal is less than a time length for the first time selection signal line to receive the valid level signal; and
a sum of a time length for the (4m−1) th control signal line to receive the valid level signal and a time length for the (4m) th control signal line to receive the valid level signal is less than a time length for the second time-length selection signal line to receive the valid level signal.
13. The method according to claim 1 , wherein:
the display panel further comprises: 2M control signal lines, the m th row of pixel circuits are connected to a (2m−1) th control signal line and a (2m) th control signal line respectively, and M is a total number of rows of the pixel circuits;
the method further comprises: providing a valid level signal to the control signal lines; and
in a case that the m th row of pixel units are used for display, time for the (2m−1) th control signal line to receive the valid level signal and time for the (2m) th control signal line to receive the valid level signal are within the time for the reset signal line connected to the m th row of pixel circuits to receive the valid level signal, and the time for the (2m−1) th control signal line to receive the valid level signal and the time for the (2m) th control signal line to receive the valid level signal are not overlapped.
14. The method according to claim 13 , wherein:
within the time for the reset signal line connected to at least one row of pixel circuits to receive the valid level signal, the valid level signal received by the first time-length control signal line comprises two first pulse signals, and the valid level signal received by the second time-length control signal line comprises two second pulse signals, the first pulse signals and the second pulse signals are alternately produced.
15. The method according to claim 14 , wherein:
time for the first time-length control signal line to receive one of the first pulse signals is within time for one of the control signal lines connected to at least one row of pixel circuits to receive the valid level signal in a case that the at least one row of pixel circuits are used for display, and time for the first time-length control signal line to receive another first pulse signal is within time for another control signal line connected to at least one row of pixel circuits to receive the valid level signal in a case that the at least one row of pixel circuits are used for display.
16. The method according to claim 15 , wherein:
time for the second time-length control signal line to receive one of the second pulse signals is within the time for one of the control signal lines connected to at least one row of pixel circuits to receive the valid level signal in a case that the at least one row of pixel circuits are used for display, and time for the second time-length control signal line to receive another second pulse signal is within the time for another control signal line connected to at least one row of pixel circuits to receive the valid level signal in a case that the at least one row of pixel circuits are used for display.
17. The method according to claim 14 , wherein:
a sum of a time length for the first pulse signal and a time length for the second pulse signal within the time for one of the control signal lines connected to at least one row of pixel circuits to receive the valid level signal in a case that the at least one row of pixel circuits are used for display is less than a time length for one of the control signal lines connected to at least one row of pixel circuits to receive the valid level signal in a case that the at least one row of pixel circuits are used for display.
18. The method according to claim 17 , wherein:
a sum of the time length for the first pulse signal and the time length for the second pulse signal within the time for another control signal line connected to at least one row of pixel circuits to receive the valid level signal in a case that the at least one row of pixel circuits are used for display is less than a time length for another control signal line connected to at least one row of pixel circuits to receive the valid level signal in a case that the at least one row of pixel circuits are used for display.