Ferroelectric field effect transistors based approach for Euclidean distance calculation in neuromorphic hardware
An apparatus may comprise a synapse comprising a first reconfigurable field-effect transistor; a second reconfigurable field-effect transistor connected in parallel to the first reconfigurable field-effect transistor; an input voltage applied to each of the first reconfigurable field-effect transistor and the second reconfigurable field-effect transistor corresponding to an input attribute associated with an error computation; and a current sensor measures a saturation drain current of the first reconfigurable field-effect transistor and the second reconfigurable field-effect transistor and determines a Euclidean error based on the saturation drain current of the FETs.
1 . An apparatus comprising a synapse comprising:
a first reconfigurable field-effect transistor comprising an n-channel or p-channel ferroelectric field-effect transistor with a first gate voltage being an input voltage or a weight voltage and a first threshold voltage being based on the weight voltage or the input voltage; and
a second reconfigurable field-effect transistor connected in parallel to the first reconfigurable field-effect transistor and comprising an n-channel or p-channel ferroelectric field-effect transistor with a second gate voltage being the weight voltage or the input voltage and a second threshold voltage being based on the input voltage or the weight voltage, wherein
the input voltage is applied to a gate of at least one of the first reconfigurable field-effect transistor and the second reconfigurable field-effect transistor, the input voltage corresponding to an input attribute associated with an error computation; and
a current sensor measuring a saturation drain current of the first reconfigurable field-effect transistor or the second reconfigurable field-effect transistor, and determining a Euclidean error based on the saturation drain current of the first reconfigurable field-effect transistor or the second reconfigurable field-effect transistor.
2 . The apparatus of claim 1 , further comprising a threshold voltage programming circuit configured to update the first threshold voltage and/or the second threshold voltage.
3 . The apparatus of claim 1 , wherein:
the first reconfigurable field-effect transistor comprises an n-channel ferroelectric field-effect transistor with the first gate voltage being the input voltage and the first threshold voltage programmed to the weight voltage; and
the second reconfigurable field-effect transistor comprises an n-channel ferroelectric field-effect transistor with the second gate voltage being the weight voltage and the second threshold voltage programmed to the input voltage.
4 . The apparatus of claim 1 , wherein:
the first reconfigurable field-effect transistor comprises a p-channel ferroelectric field-effect transistor with the first gate voltage being the weight voltage and the first threshold voltage programmed to the input voltage minus a source voltage; and
the second reconfigurable field-effect transistor comprises a p-channel ferroelectric field-effect transistor with the second gate voltage being the input voltage and the second threshold voltage programmed to the weight voltage minus the source voltage.
5 . The apparatus of claim 1 , wherein:
the first reconfigurable field-effect transistor comprises an n-channel ferroelectric field-effect transistor with the first gate voltage being the input voltage and the first threshold voltage programmed to the weight voltage; and
the second reconfigurable field-effect transistor comprises a p-channel ferroelectric field-effect transistor with the second gate voltage being the input voltage and the second threshold voltage programmed to the first threshold voltage of the first reconfigurable field-effect transistor minus a supply voltage.
6 . The apparatus of claim 1 , wherein a plurality of synapses comprises a two-dimensional grid of the synapses configured to compute multiple Euclidean errors.
7 . The apparatus of claim 1 , wherein a plurality of synapses comprises a three-dimensional grid of the synapses configured to compute multiple Euclidean errors.
8 . The apparatus of claim 1 , further comprising:
a plurality of instances of the synapse arranged in a two-dimensional grid comprising a plurality of synapses, each synapse of the plurality of synapses corresponding to a neuron of a self-organizing feature map, wherein a weight associated with the neuron is stored such that a threshold voltage of at least one of the first reconfigurable field-effect transistor and the second reconfigurable field-effect transistor is based on the weight, and the input voltage applied to each synapse of the plurality of synapses corresponds to an input attribute of the self-organizing feature map;
a best matching unit selection circuit configured to determine a best matching neuron based on the saturation drain current of at least one of the first reconfigurable field-effect transistor and the second reconfigurable field-effect transistor of at least one synapse of the plurality of synapses; and
a threshold voltage programming circuit configured to update the threshold voltage of at least one of the first reconfigurable field-effect transistor and the second reconfigurable field-effect transistor of at least one synapse of the plurality of synapses based on the best matching neuron.
9 . The apparatus of claim 8 , wherein the saturation drain current of one of the reconfigurable field-effect transistors of each synapse corresponds to a Euclidean error between the input attribute and the weight associated with each neuron.
10 . The apparatus of claim 8 , wherein:
the first reconfigurable field-effect transistor comprises an n-channel ferroelectric field-effect transistor with the first gate voltage being the input voltage and the first threshold voltage programmed to the weight voltage, the weight voltage corresponding to the weight; and
the second reconfigurable field-effect transistor comprises an n-channel ferroelectric field-effect transistor with the second gate voltage being the weight voltage and the second threshold voltage programmed to the input voltage.
11 . The apparatus of claim 8 , wherein:
the first reconfigurable field-effect transistor comprises an n-channel ferroelectric field-effect transistor with the first gate voltage being the input voltage and the first threshold voltage programmed to the weight voltage, the weight voltage corresponding to the weight; and
the second reconfigurable field-effect transistor comprises a p-channel ferroelectric field-effect transistor with the second gate voltage being the input voltage and the second threshold voltage programmed to the first threshold voltage minus a supply voltage.
12 . The apparatus of claim 8 , wherein:
a current for each synapse is accumulated in a capacitor associated with the synapse; and
the best matching unit selection circuit comprises complementary metal-oxide semiconductor logic that identifies a neuron whose associated capacitor is last to charge to logic 1.
13 . The apparatus of claim 8 , further comprising a best matching input neuron labeling circuit configured to determine a best matching input for each neuron.
14 . The apparatus of claim 13 , wherein the best matching input neuron labeling circuit comprises:
a voltage comparator to determine if an error from a current input is lower than a current best matching input;
a capacitor charged from an error of the best matching input;
a third transistor configured to charge the capacitor; and
a fourth transistor configured to discharge the capacitor.
15 . The apparatus of claim 13 , wherein the best matching input neuron labeling circuit further comprises:
a voltage comparator to determine if an error from a current input is lower than a current best matching input;
a first capacitor charged by the current input;
a second capacitor charged from an error of the best matching input;
a first transistor configured to discharge the first capacitor between each input;
a second transistor configured to charge the first capacitor when a new input is provided;
a third transistor configured to discharge a previous best matching input stored in the second capacitor when a new best matching input is found; and
a fourth transistor configured to update the new best matching input on the second capacitor.
16 . The apparatus of claim 8 , wherein the saturation drain current of one of the reconfigurable field-effect transistors of each synapse corresponds to a value of the input attribute minus the weight associated with the neuron that corresponds to the synapse, all raised to a first power, wherein the first power has a value between 1 and 2 based on one or more parameters of the reconfigurable field-effect transistors.
17 . The apparatus of claim 1 , wherein the first reconfigurable field-effect transistor and the second reconfigurable field-effect transistor each comprises a ferroelectric field-effect transistor.
18 . A method comprising:
receiving an input voltage corresponding to an input attribute of a self-organizing feature map;
applying the input voltage to each synapse of a two-dimensional grid of synapses, each synapse corresponding to a neuron of the self-organizing feature map, and comprising two reconfigurable field-effect transistors, wherein a weight associated with the neuron is stored such that a threshold voltage of at least one of the reconfigurable field-effect transistors is based on the weight;
determining a best matching neuron based on a saturation drain current of at least one of the reconfigurable field-effect transistors of each synapse; and
updating the threshold voltage of at least one of the reconfigurable field-effect transistors of at least one synapse of the two-dimensional grid of synapses based on the best matching neuron.
19 . The method of claim 18 , wherein:
a first reconfigurable field-effect transistor of the two reconfigurable field-effect transistors comprises an n-channel ferroelectric field-effect transistor with a first gate voltage being the input voltage and a first threshold voltage programmed to a weight voltage; and
a second reconfigurable field-effect transistor of the two reconfigurable field-effect transistors comprises an n-channel ferroelectric field-effect transistor with a second gate voltage being the weight voltage and a second threshold voltage programmed to the input voltage.
20 . The method of claim 18 , wherein:
a first reconfigurable field-effect transistor of the two reconfigurable field-effect transistors comprises an n-channel ferroelectric field-effect transistor with a first gate voltage being the input voltage and a first threshold voltage programmed to a weight voltage; and
a second reconfigurable field-effect transistor of the two reconfigurable field-effect transistors comprises a p-channel ferroelectric field-effect transistor with a second gate voltage being the input voltage and a second threshold voltage programmed to the first threshold voltage minus a supply voltage.