Adaptive bias decoder for non-volatile memory system
In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to an erase gate line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line in response to changes in a voltage of the source line.
1 . A non-volatile memory system, comprising:
an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain;
a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells;
a source line coupled to the source of each non-volatile memory cell in a row; and
an adaptive bias decoder coupled to the source line and an erase gate line of the array to generate a voltage and apply the voltage to the erase gate line during an operation;
wherein the adaptive bias decoder comprises an adjustable resistor comprising a first end and a second end, the first end coupled to an adjustable current source to provide the voltage and the second end coupled to the source line, wherein the adaptive bias decoder adjusts a resistance of the adjustable resistor to thereby adjust the voltage in response to changes in a voltage of the source line.
2 . The non-volatile memory system of claim 1 , wherein the non-volatile memory system further comprises a voltage regulator coupled to the first end of the resistor.
3 . The non-volatile memory system of claim 2 , wherein the adaptive bias decoder further comprises a digital-to-analog converter for converting a digital input to an analog signal applied to the erase gate line.
4 . The non-volatile memory system of claim 1 , wherein the operation is a read operation.
5 . The non-volatile memory system of claim 1 , wherein the operation is a program operation.
6 . The non-volatile memory system of claim 1 , wherein the adaptive bias decoder further comprises an analog-to-digital converter.
7 . The non-volatile memory system of claim 1 , comprising:
a plurality of pull down bit lines, each of the plurality of pull down bit lines coupling the source line to a pull down node.