Method and apparatus for configuring array columns and rows for accessing flash memory cells
In one embodiment of the present invention, one row is selected and two columns are selected for a read or programming operation, such that twice as many flash memory cells can be read from or programmed in a single operation compared to the prior art. In another embodiment of the present invention, two rows in different sectors are selected and one column is selected for a read operation, such that twice as many flash memory cells can be read in a single operation compared to the prior art.
1. A non-volatile memory device comprising:
an array of split gate flash memory cells comprising a plurality of split gate flash memory cells organized into rows and columns, wherein the array is further organized into a plurality of sectors, each sector comprising a plurality of rows of split gate flash memory cells; and
a row decoder selectively coupled to a first sector within the plurality of sectors and a second sector within the plurality of sectors;
wherein during a read operation, the row decoder selects one row of split gate flash memory cells in the first sector and one row of split gate flash memory cells in the second sector such that when a single column is selected, a read operation is performed on two split gate flash memory cells; and
wherein programming of the selected row of the first sector and programming of the selected row of the second sector occur at the same time.
2. A non-volatile memory device comprising:
an array of flash memory cells comprising a plurality of flash memory cells organized into rows and columns, wherein the array is further organized into plurality of sectors, each sector comprising a plurality of rows of flash memory cells;
a row decoder selectively coupled to a first sector within the plurality of sectors and a second sector within the plurality of sectors; and
a differential sense amplifier selectively coupled to the first sector and the second sector;
wherein during a read operation, the row decoder selects a first row of flash memory cells in the first sector and a second row of flash memory cells in the second sector and when a single column is selected the differential sense amplifier determines the difference in values stored by a selected flash memory cell in the first row and the single column and a selected flash memory cell in the second row and the single column, where the two selected flash memory cells are erased flash memory cells.
3. The non-volatile memory device of claim 2 , where an output of the differential sense amplifier is a ‘1’.
4. A non-volatile memory device comprising:
an array of flash memory cells comprising a plurality of flash memory cells organized into rows and columns, wherein the array is further organized into plurality of sectors, each sector comprising a plurality of rows of flash memory cells;
a row decoder selectively coupled to a first sector within the plurality of sectors and a second sector within the plurality of sectors; and
a differential sense amplifier selectively coupled to the first sector and the second sector;
wherein during a read operation, the row decoder selects a first row of flash memory cells in the first sector and a second row of flash memory cells in the second sector and when a single column is selected the differential sense amplifier determines the difference in values stored by a selected flash memory cell in the first row and the single column and a selected flash memory cell in the second row and the single column, the differential sense amplifier comprising:
a first circuit coupled to the selected flash memory cell in the first sector;
a second circuit coupled to the selected flash memory cell in the second sector; and
a comparator coupled to the first circuit and second circuit to determine a difference in values stored in the selected flash memory cell in the first sector and the selected flash memory cell in the second sector;
wherein the first circuit comprises a first input transistor and the second circuit comprises a second input transistor, the first input transistor and second input transistor having different widths.
5. A non-volatile memory device comprising:
an array of flash memory cells comprising a plurality of flash memory cells organized into rows and columns, wherein the array is further organized into plurality of sectors, each sector comprising a plurality of rows of flash memory cells;
a row decoder selectively coupled to a first sector within the plurality of sectors and a second sector within the plurality of sectors; and
a differential sense amplifier selectively coupled to the first sector and the second sector;
wherein during a read operation, the row decoder selects a first row of flash memory cells in the first sector and a second row of flash memory cells in the second sector and when a single column is selected the differential sense amplifier determines the difference in values stored by a selected flash memory cell in the first row and the single column and a selected flash memory cell in the second row and the single column, the differential sense amplifier comprising:
a first circuit coupled to the selected flash memory cell in the first sector;
a second circuit coupled to the selected flash memory cell in the second sector; and
a comparator coupled to the first circuit and second circuit to determine a difference in values stored in the selected flash memory cell in the first sector and the selected flash memory cell in the second sector;
wherein the first circuit comprises a first input transistor and the second circuit comprises a second input transistor, the first input transistor and second input transistor having different lengths.