Granted Patent B2

US 10,340,010 · App. 15/238,681 · Granted Jul 2, 2019

Inventors: Hieu Van Tran (San Jose, CA); Anh Ly (San Jose, CA); Thuan Vu (San Jose, CA); Vipin Tiwari (Dublin, CA); Nhan Do (Saratoga, CA)

Assignee: SILICON STORAGE TECHNOLOGY, INC.

G11C16/08G11C16/0425G11C16/10G11C16/14G11C16/24G11C16/26G11C16/28G11C16/32G11C16/3418G11C16/3427G11C2216/04G11C2216/22

Abstract

Claims (8)

1. A non-volatile memory device comprising:

an array of flash memory cells comprising a plurality of flash memory cells organized into rows and columns, wherein the array is further organized into a plurality of sectors, each sector comprising a plurality of rows of flash memory cells;

a first column decoder selectively coupled to a first sector configured to operate in dual-column mode; and

a second column decoder selectively coupled to a second sector configured to operate in single-column mode;

wherein during a read or programming operation in the first sector, the first column decoder selects two immediately adjacent columns enabling reading or programming of two immediately adjacent flash memory cells and during a read or programming operation in the second sector, the second column decoder selects no more than one column enabling reading or programming of one flash memory cell.

2. The non-volatile memory device of claim 1 , wherein the memory cells are split gate flash memory cells.

3. The non-volatile memory device of claim 1 , wherein during a programming operation in the first sector, programming of the selected two columns occurs at different times.

4. The non-volatile memory device of claim 2 , wherein during a programming operation in the first sector, programming of the selected two columns occurs at different times.

Assignments (17)

Continuity (1)