Granted Patent B2

US 12,518,829 · App. 18/536,186 · Granted Jan 6, 2026

Inventors: Hieu Van Tran (San Jose, CA); Thuan Vu (San Jose, CA); Stanley Hong (San Jose, CA); Stephen Trinh (San Jose, CA); Anh Ly (San Jose, CA); Nhan Do (Saratoga, CA); Mark Reiten (Alamo, CA)

Assignee: Silicon Storage Technology, Inc.

G11C16/08G11C11/54G11C16/24G11C2216/04

Abstract

Claims (10)

1 . A non-volatile memory system, comprising:

an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain, the array comprising a reference node;

a source line coupled to the source of each non-volatile memory cell in a row of non-volatile memory cells in the array;

an adaptive bias circuit for generating a reference voltage that varies in response to a change in a voltage of the reference node; and

a digital-to-analog converter for converting a digital input comprising one of N possible values, where N>2, into an analog voltage using the voltage of the reference node and the reference voltage and providing the analog voltage to the source line during a program operation to program the one of N possible values into a selected non-volatile memory cell in the array.

2 . The non-volatile memory system of claim 1 , wherein the adaptive bias circuit adjusts the reference voltage in response to changes in temperature.

3 . The non-volatile memory system of claim 2 , wherein the non-volatile memory cells are split-gate flash memory cells.

4 . The non-volatile memory system of claim 2 , wherein the non-volatile memory cells are stacked-gate flash memory cells.

5 . The non-volatile memory system of claim 1 , wherein the non-volatile memory cells are split-gate flash memory cells.

6 . The non-volatile memory system of claim 1 , wherein the non-volatile memory cells are stacked-gate flash memory cells.

Assignments (2)

Continuity (3)

References Cited (29)