Method for manufacturing semiconductor-element-containing memory device
View Patent ↗A two-stage dynamic flash memory is formed as follows. An N + layer 20 is formed in a pillar-shaped semiconductor layer 12 , which stands on an N + layer 2 a , by performing a heat treatment, thereby producing an effect of forcing a donor impurity out into the pillar-shaped semiconductor layer 12 from a silicide layer 18 , which is a layer formed to surround a middle portion of the pillar-shaped semiconductor layer 12 and contains the donor impurity. Gate oxide layers 19 a to 19 d are formed on a side surface of the pillar-shaped semiconductor layer 12 . Etching is performed with a single mask to form first to fourth gate conductor layers 21 aa, 22 aa, 22 ba , and 21 ba and a silicide layer 18 a , which have the same shape as viewed in plan view. An N + layer 23 is formed on a top portion of the pillar-shaped semiconductor layer 12.
1 . A method for manufacturing a semiconductor-element-containing memory device that includes a first memory cell configured to perform a data write operation, a data read operation, and a data erase operation by using a voltage that is applied to a first wiring layer, a second wiring layer, and a third wiring layer, the first wiring layer being connected to a first impurity layer, the second wiring layer being connected to a first gate conductor layer, a second gate conductor layer, and a second impurity layer, the third wiring layer being connected to a third gate conductor layer, a fourth gate conductor layer, and a third impurity layer, the method comprising the steps of:
forming the first impurity layer over a substrate and forming, over the first impurity layer, in a layered manner, a first insulating layer, a first material layer, a second insulating layer, a second material layer, a third insulating layer, a third material layer, a fourth insulating layer, a fourth material layer, a fifth insulating layer, a fifth material layer, and a sixth insulating layer, which are disposed in this order, starting from a lower position;
forming a first hole extending through the first to sixth insulating layers and the first to fifth material layers in a vertical direction and having a bottom portion in the first impurity layer;
filling the first hole with a first pillar-shaped semiconductor layer;
removing the third material layer to form a first space;
forming a first semiconductor layer in contact with an inner wall of the first space with a portion of the first space being left unfilled, the first semiconductor layer containing a donor impurity or an acceptor impurity;
forming a first alloy layer that is made of an alloy or a metal and fills the portion of the first space that is inside the first semiconductor layer:
performing a heat treatment, thereby causing the first semiconductor layer and the first alloy layer to be integrated with each other to form a second alloy layer and also causing the donor impurity or the acceptor impurity of the first semiconductor layer to diffuse into the first pillar-shaped semiconductor layer to form the second impurity layer;
removing the first material layer, the second material layer, the fourth material layer, and the fifth material layer to form a second space and forming a first gate insulating layer that covers at least an exposed portion of a side surface of the first pillar-shaped semiconductor layer in the second space;
forming a first conductor layer, a second conductor layer, a third conductor layer, and fourth conductor layer, which are disposed in this order, starting from a lower position, and fill the second space;
etching, with a single mask, the second alloy layer, the first to fourth conductor layers, and the second to sixth insulating layers to form the first to fourth gate conductor layers and the second wiring layer such that the first to fourth gate conductor layers and the second wiring layer have substantially a same shape as viewed in plan view;
forming the third impurity layer on a top portion of the first pillar-shaped semiconductor layer; and
forming the third wiring layer that is connected to the third impurity layer, the third wiring layer extending in a same direction as the first wiring layer and being perpendicular to the second wiring layer, as viewed in plan view.
2 . The method for manufacturing a semiconductor-element-containing memory device according to claim 1 , further comprising the step of connecting the first wiring layer to a first bit line, connecting the second wiring layer to a common source line, and connecting the third wiring layer to a second bit line.
3 . The method for manufacturing a semiconductor-element-containing memory device according to claim 1 , further comprising the steps of:
connecting one of the first gate conductor layer and the second gate conductor layer to a first plate line and connecting another of the first gate conductor layer and the second gate conductor layer to a first word line;
connecting the third gate conductor layer to one of a second plate line and a second word line that has a same driving purpose as the second gate conductor layer; and
connecting the fourth gate conductor layer to one of the second plate line and the second word line that has a same driving purpose as the first gate conductor layer.
4 . The method for manufacturing a semiconductor-element-containing memory device according to claim 1 , wherein the forming of the first to fourth conductor layers that fill the second space is performed before the forming of the second alloy layer.
5 . The method for manufacturing a semiconductor-element-containing memory device according to claim 1 , wherein the forming of the first to fourth conductor layers that fill the second space is performed after the forming of the second alloy layer.
6 . The method for manufacturing a semiconductor-element-containing memory device according to claim 1 , wherein the first semiconductor layer comprises a donor impurity or an acceptor impurity and comprises at least silicon atoms.
7 . The method for manufacturing a semiconductor-element-containing memory device according to claim 1 , wherein the first alloy layer comprises at least nickel atoms.
8 . The method for manufacturing a semiconductor-element-containing memory device according to claim 1 , wherein the first and fourth gate conductor layers and one or both of the second and third gate conductor layers are formed to each comprise a plurality of layers disposed in the vertical direction.
9 . The method for manufacturing a semiconductor-element-containing memory device according to claim 1 , wherein the first to fourth gate conductor layers and the second wiring layer are formed to each comprise two layers having a same shape as viewed in plan view.
10 . The method for manufacturing a semiconductor-element-containing memory device according to claim 1 , wherein the first to fourth gate conductor layers are formed to have a same height in the vertical direction.
11 . The method for manufacturing a semiconductor-element-containing memory device according to claim 1 , further comprising forming a second memory cell over the first pillar-shaped semiconductor layer with a process that is substantially a same as the process for the first memory cell and by using the third impurity layer as a common impurity layer, the second memory cell having a structure in which upper and lower positions are reversed in the vertical direction compared to the upper and lower positions of the first memory cell, the method comprising the steps of:
forming the third wiring layer such that the third wiring layer is connected to a side surface of the third impurity layer and extends in a direction perpendicular to the second conductor layer as viewed in plan view;
forming a second pillar-shaped semiconductor layer over the third impurity layer;
forming a fifth gate conductor layer, a sixth gate conductor layer, a fourth wiring layer, a seventh gate conductor layer, and an eighth gate conductor layer, which are disposed in this order, starting from a lower position, and are isolated from one another, the fourth wiring layer being connected to a fourth impurity layer formed in the second pillar-shaped semiconductor layer;
forming a second gate insulating layer that is disposed between the second pillar-shaped semiconductor layer and the fifth to eighth gate conductor layers;
forming a fifth impurity layer on a top portion of the second pillar-shaped semiconductor layer; and
forming a fifth wiring layer that is connected to the fifth impurity layer and extends in a same direction as the third wiring layer, as viewed in plan view,
wherein the fifth to eighth gate conductor layers and the fourth wiring layer are formed to substantially have a same shape as and overlap with the first to fourth gate conductor layers and the second wiring layer, as viewed in plan view.
12 . The method for manufacturing a semiconductor-element-containing memory device according to claim 11 , further comprising the steps of:
connecting the third wiring layer to a common bit line of the first and second memory cells;
connecting one of the fifth gate conductor layer and the sixth gate conductor layer to a third plate line and connecting another of the fifth gate conductor layer and the sixth gate conductor layer to a third word line;
connecting the seventh gate conductor layer to one of a fourth plate line and a fourth word line that has a same driving purpose as the sixth gate conductor layer; and
connecting the eighth gate conductor layer to one of the fourth plate line and the fourth word line that has a same driving purpose as the fifth gate conductor layer.
13 . The method for manufacturing a semiconductor-element-containing memory device according to claim 1 , wherein the first wiring layer is formed to surround a portion or an entirety of an outer peripheral portion of a bottom portion of the first pillar-shaped semiconductor layer, as viewed in plan view, and to be connected to the first impurity layer.
14 . The method for manufacturing a semiconductor-element-containing memory device according to claim 1 , wherein the first to fourth gate conductor layers and the second wiring layer have a same shape and extend two-dimensionally, as viewed in plan view, and are connected to adjacent memory cells.
15 . The method for manufacturing a semiconductor-element-containing memory device according to claim 1 , wherein
the first and fourth gate conductor layers are formed to each comprise a plurality of gate electrode conductor layers that constitute a first drain-side select gate conductor layer, a plurality of first word line gate conductor layers, a first source-side select gate conductor layer, a second source-side select gate conductor layer, a plurality of second word line gate conductor layers, and a second drain-side select gate conductor layer, which are disposed in this order, starting from a lower position,
the first pillar-shaped semiconductor layer is formed to include or not to include an insulating layer in a middle portion, and
the first insulating layer is formed to include a floating conductor layer or a charge trap layer, the first insulating layer surrounding the first pillar-shaped semiconductor layer and the first and second word line gate conductor layers, the floating conductor layer being electrically isolated from the first pillar-shaped semiconductor layer and the first and second word line gate conductor layers, the charge trap layer being made of an insulating layer.
16 . The method for manufacturing a semiconductor-element-containing memory device according to claim 15 , wherein the first drain-side select gate conductor layer and the second drain-side select gate conductor layer each comprise a plurality of gate conductor layers.