Semiconductor integrated circuit, semiconductor device, and semiconductor memory device
According to one embodiment, a clock signal is input to clock terminals of first and second flip-flops of a semiconductor integrated circuit. A first signal output from a Q terminal of the second flip-flop is input to a D terminal of the first flip-flop. An inverter inverts a second signal output from a Q terminal of the first flip-flop, and a third signal obtained by inverting the second signal is input to a D terminal of the second flip-flop. Adders respectively operate on different bits of a gray code by performing addition based on an input carry signal. A circuit block generates a carry signal to be input to a first adder by performing an AND operation of the first and third signals. The circuit block generates a carry signal to be input to other adders based on the first and second signals.
1 . A semiconductor integrated circuit configured to generate an L-bit, wherein L is an integer of 3 or more gray code according to a count value of a first clock signal, the semiconductor integrated circuit comprising:
a first flip-flop including a clock terminal to which the first clock signal is configured to be input;
a second flip-flop including a clock terminal to which the first clock signal is configured to be input, a first signal output from a Q terminal of the second flip-flop being input to a D terminal of the first flip-flop;
an inverter configured to perform an inversion operation on a second signal output from a Q terminal of the first flip-flop, a third signal obtained by inverting the second signal output from the inverter being input to a D terminal of the second flip-flop;
(L−1) adders, each configured to respectively generate and operate on a different bit of the gray code by performing addition based on a respective bit of an input carry signal;
a circuit block configured to generate the input carry signal and output a first bit of the input carry signal to a first adder of the (L−1) adders by performing an AND operation of the first signal and the third signal, and output a respective bit of the remaining bit or bits of the input carry signal to each of a second adder to an (L−1)th adder of the (L−1) adders based on the first signal and the second signal;
a first terminal configured to output the first signal; and
(L−1) second terminals configured to output a set of signals output from the (L−1) adders.
2 . The semiconductor integrated circuit according to claim 1 , wherein;
each of the (L−1) adders includes:
a third flip-flop; and
an exclusive OR circuit configured to perform an exclusive OR operation of an input carry signal and a fourth signal output from a Q terminal of the third flip-flop, and input a signal obtained by the exclusive OR operation to a D terminal of the third flip-flop, and wherein
the (L−1) second terminals are configured to output a set of fourth signals of the respective (L−1) adders.
3 . The semiconductor integrated circuit according to claim 2 , wherein the circuit block is configured to invert the first signal, perform an AND operation of the second signal and a fifth signal obtained by inverting the first signal, and generate a respective one of the input carry signal to be output to the second adder of the (L−1) adders by performing an AND operation of a fourth signal from the first adder and a sixth signal obtained by performing an AND operation of the fifth signal and the second signal.
4 . A semiconductor device comprising:
the semiconductor integrated circuit according to claim 1 ;
an oscillator circuit configured to generate a second clock signal; and
a register configured to store therein the gray code output from the first terminal and the (L−1) second terminals of the semiconductor integrated circuit at timing based on the second clock signal.
5 . A semiconductor device comprising:
the semiconductor integrated circuit according to claim 2 ;
an oscillator circuit configured to generate a second clock signal; and
a register configured to store therein the gray code output from the first terminal and the (L−1) second terminals of the semiconductor integrated circuit at timing based on the second clock signal.
6 . A semiconductor device comprising:
the semiconductor integrated circuit according to claim 3 ;
an oscillator circuit configured to generate a second clock signal; and
a register configured to store therein the gray code output from the first terminal and the (L−1) second terminals of the semiconductor integrated circuit at timing based on the second clock signal.
7 . A semiconductor memory device comprising:
the semiconductor device according to claim 4 ; and
a memory chip, wherein
the first clock signal is a data strobe signal for transfer of data that is transferred to or from the memory chip, and
the semiconductor device further includes a control circuit configured to control, based on the gray code stored in the register, the oscillator circuit such that a frequency of the second clock signal becomes equal to or higher than a frequency of the data strobe signal.
8 . A semiconductor memory device comprising:
the semiconductor device according to claim 5 ; and
a memory chip, wherein
the first clock signal is a data strobe signal for transfer of data that is transferred to or from the memory chip, and
the semiconductor device further includes a control circuit configured to control, based on the gray code stored in the register, the oscillator circuit such that a frequency of the second clock signal becomes equal to or higher than a frequency of the data strobe signal.
9 . A semiconductor memory device comprising:
the semiconductor device according to claim 6 ; and
a memory chip, wherein
the first clock signal is a data strobe signal for transfer of data that is transferred to or from the memory chip, and
the semiconductor device further includes a control circuit configured to control, based on the gray code stored in the register, the oscillator circuit such that a frequency of the second clock signal becomes equal to or higher than a frequency of the data strobe signal.
10 . The semiconductor memory device according to claim 7 , wherein the memory chip includes a nonvolatile memory.
11 . The semiconductor memory device according to claim 8 , wherein the memory chip includes a nonvolatile memory.
12 . The semiconductor memory device according to claim 9 , wherein the memory chip includes a nonvolatile memory.
13 . The semiconductor memory device according to claim 10 , wherein the nonvolatile memory includes a NAND flash memory.
14 . The semiconductor memory device according to claim 11 , wherein the nonvolatile memory includes a NAND flash memory.
15 . The semiconductor memory device according to claim 12 , wherein the nonvolatile memory includes a NAND flash memory.
16 . The semiconductor integrated circuit according to claim 3 , wherein the circuit block is configured to invert the fourth signal from the first adder, perform an AND operation of the sixth signal and a seventh signal obtained by inverting the fourth signal, and generate a respective one of the input carry signal to be output to the third adder that is next to the second adder of the (L−1) adders by performing an AND operation of a fourth signal from the second adder and an eighth signal obtained by performing an AND operation of the seventh signal and the sixth signal.
17 . A semiconductor device comprising:
the semiconductor integrated circuit according to claim 16 ;
an oscillator circuit configured to generate a second clock signal; and
a register configured to store therein the gray code output from the first terminal and the (L−1) second terminals of the semiconductor integrated circuit at timing based on the second clock signal.
18 . A semiconductor memory device, comprising:
the semiconductor device according to claim 17 ; and
a memory chip, wherein
the first clock signal is a data strobe signal for transfer of data that is transferred to or from the memory chip, and
the semiconductor device further includes a control circuit configured to control, based on the gray code stored in the register, the oscillator circuit such that a frequency of the second clock signal becomes equal to or higher than a frequency of the data strobe signal.
19 . The semiconductor memory device according to claim 18 , wherein the memory chip includes a nonvolatile memory.
20 . The semiconductor memory device according to claim 19 , wherein the nonvolatile memory includes a NAND flash memory.