Fast-locking phase-locked loop, transceiver, and communication device
A fast-locking phase-locked loop comprises a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a frequency divider, and a fast-locking control unit which receives a reference clock signal at its first input terminal and a phase-locking enable signal at its second input terminal and outputs a reset signal at a high level in response to a rising edge of the reference clock signal when receiving the phase-locking enable signal, wherein the frequency divider is connected to an output terminal of the fast-locking control unit and configured to trigger generation of a feedback signal in response to the reset signal at the high level, and the phase frequency detector is connected to the output terminal of the fast-locking control unit and configured to output a phase error between the reference clock signal and the feedback signal in response to the reset signal at the high level.
1. A fast-locking phase-locked loop, comprising a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider, and further comprising:
a fast-locking control unit that has a first input terminal for receiving a reference clock signal and a second input terminal for receiving a phase-locking enable signal and is configured to shift an outputted reset signal from a low level to a high level in response to a rising edge of the reference clock signal, when the received phase-locking enable signal is at a high level, so as to reduce an initial phase error between the reference clock signal and a feedback signal,
wherein the frequency divider is connected to an output terminal of the fast-locking control unit and configured to trigger generation of the feedback signal in response to the reset signal at the high level; and
the phase frequency detector is connected to the output terminal of the fast-locking control unit and configured to output a phase error between the reference clock signal and the feedback signal in response to the reset signal at the high level.
2. The phase-locked loop according to claim 1 , wherein the fast-locking control unit is configured to output the reset signal at the low level when the phase-locking enable signal is at a low level; and shift the reset signal from the low level to the high level at the rising edge of the reference clock signal when the phase-locking enable signal is at a high level.
3. The phase-locked loop according to claim 1 , wherein the fast-locking control unit comprises a rising edge triggered D-type flip-flop.
4. The phase-locked loop according to claim 3 , wherein the D-type flip-flop has a D terminal for receiving the phase-locking enable signal, a CLK terminal for receiving the reference clock signal, a reset terminal for receiving the phase-locking enable signal, and a Q terminal functioning as an output terminal.
5. The phase-locked loop according to claim 1 , wherein the fast-locking control unit comprises a plurality of cascaded D-type flip-flops.
6. The phase-locked loop according to claim 5 , wherein the fast-locking control unit comprises two cascaded D-type flip-flops, such that the fast-locking control unit outputs the reset signal at the high level at the second rising edge of the reference clock signal.
7. The phase-locked loop according to claim 1 , wherein the phase frequency detector is configured to reset phase error signals UP and DN to 0 in response to the reset signal at the low level.
8. The phase-locked loop according to claim 1 , wherein the frequency divider is configured to reset the feedback signal to a low level in response to the reset signal at the low level, and output the feedback signal based on a period of an output signal of the voltage-controlled oscillator and the number N of voltage dividers in response to the reset signal at the high level.
9. A fast-locking transceiver, comprising a phase-locked loop according to claim 1 .