IP Library › Granted Patent US 12,468,642
Granted Patent B2
US 12,468,642 · App. 18/540,258 · Granted Nov 11, 2025

Serial bus communication without read indication

Inventors: Jens Barrenscheen (Munich, DE); Heimo Hartlieb (Graz, AT)
Assignee: Infineon Technologies AG
G06F13/1668G06F13/4282H04L45/74
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Quick Facts
Patent No.
US 12,468,642
App. No.
18/540,258
Granted
Nov 11, 2025
Kind
B2
Abstract

A method for a responder bus node is described herein. In accordance with one embodiment, the method includes receiving a first frame over a first data channel of a serial bus, wherein the first frame comprises at least a first header field with first header data and a first payload field with first payload data. The method further includes checking whether a first address, which is based on the first header data, is equal to a predetermined address. When the first address is equal to the predetermined address, a read operation is performed using a second address, which is based on the first payload data, and, when the first address is not equal to the predetermined address, a write operation is performed using the first address and the payload data. Furthermore, a corresponding method for a commander bus node, as well as a respective responder and commander bus node are described.

Claims (32)

1 . A method comprising:

receiving a first frame over a first data channel of a serial bus, the first frame comprising at least a first header field comprising first header data and a first payload field comprising first payload data;

checking whether a first address, which is based on the first header data, is equal to a predetermined address; and

when the first address is equal to the predetermined address, performing a read operation using a second address, which is based on the first payload data, and

when the first address is not equal to the predetermined address, performing a write operation using the first address and the first payload data.

2 . The method of claim 1 ,

wherein the read operation includes reading data from the second address, which is extracted from the first payload field.

3 . The method of claim 1 ,

wherein the write operation includes writing at least parts of the first payload data to the first address.

4 . The method of claim 1 ,

wherein the checking comprises extracting the first address from the first header field and determining whether the first address is equal to the predetermined address.

5 . The method of claim 1 , further comprising:

generating a second frame, the second frame comprising at least a second payload field comprising second payload data,

wherein, the second payload data is based on data read from the second address.

6 . The method of claim 5 , further comprising:

transmitting the second frame over a second data channel of the serial bus during a second time window that is subsequent to a first time window, in which the first frame was received.

7 . A bus node comprising:

an interface circuit configured to receive a first frame over a first data channel of a serial bus, the first frame comprising at least a first header field comprising first header data and a first payload field comprising first payload data;

a frame decoder configured to check and indicate whether, or not, a first address, which is based on the first header data, is equal to a predetermined address; and

a control logic configured to:

perform a read operation using a second address, which is based on the first payload data, when the frame decoder indicates that the first address is equal to the predetermined address; and

perform a write operation using the first address and the first payload data, when the frame decoder indicates that the first address is not equal to the predetermined address.

8 . The bus node of claim 7 ,

wherein the frame decoder is configured to extract the second address from the first payload field, and

wherein to perform the read operation the control logic is configured to receive the second address from the frame decoder and to read data from the second address.

9 . The bus node of claim 7 ,

wherein to perform the write operation the control logic is configured to write at least parts of the first payload data to the first address.

10 . The bus node of claim 7 ,

wherein to check whether, or not, the first address is equal to the predetermined address, the frame decoder is configured to extract the first address to from the first header field and to determine whether the first address is equal to the predetermined address.

11 . The bus node of claim 7 , further comprising

a frame encoder configured to generate a second frame, wherein the second frame includes at least a second payload field comprising second payload data, and wherein the second payload data is based on data read from the second address.

12 . The bus node of claim 11 , wherein the frame encoder is further configured to transmit the second frame over a second data channel of the serial bus during a second time window that is subsequent to a first time window, in which the first frame was received.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2023
From: BARRENSCHEEN, JENS; HARTLIEB, HEIMO
To: INFINEON TECHNOLOGIES AG
Reel/Frame 065874/0725 →
Priority Claims (1)
DE 102023101544.3 · Jan 23, 2023 · national
Continuity (1)
Related Publication 20240248858A1 · Jul 25, 2024
References Cited (9)
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