Erroneous bit discovery in memory system
View Patent ↗Methods, systems, and devices for erroneous bit discovery in a memory system are described. A controller or memory controller, for example, may read a code word from a memory medium. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) of the memory medium. Each MSR may include a portion of memory cells of the memory medium and be associated with a counter to count a quantity of erroneous bits in each MSR. When the controller identifies a quantity of erroneous bits in the code word using an error control operation, the controller may update values of counters associated with respective MSRs that correspond to the quantity of erroneous bits to count erroneous bit counts for each MSR. In some cases, the controller may perform operations described herein as part of a background operation.
1. A method, comprising:
monitoring, by a power management component, a power level associated with a memory system;
determining that the power level varies from a first power level associated with the memory system based at least in part on monitoring the power level, wherein one or more background operations are interrupted in response to the power level varying from the first power level, and wherein the one or more background operations comprise operations independent of an access command from a host;
transmitting a signal indicating that the power level varies from the first power level based at least in part on the determination; and
resuming the one or more background operations based at least in part on information associated with the signal being restored.
2. The method of claim 1 , further comprising:
determining that the power level is below a threshold power level based at least in part on monitoring the power level, wherein determining that the power level varies from the first power level is based at least in part on the power level being below the threshold power level.
3. The method of claim 1 , wherein transmitting the signal comprises:
transmitting the signal indicating that the power level varies from the first power level to a controller associated with the memory system.
4. The method of claim 1 , further comprising:
detecting that the power level associated with the memory system indicates a power loss at the memory system based at least in part on determining that the power level varies from the first power level.
5. The method of claim 1 , further comprising:
detecting that the power level associated with the memory system indicates a power change at the memory system based at least in part on determining that the power level varies from the first power level.
6. The method of claim 1 , wherein the power level is associated with a memory medium of the memory system.
7. The method of claim 6 , wherein the memory medium comprises volatile memory cells.
8. A memory device, comprising:
a power management component;
one or more memory arrays; and
processing circuitry coupled with the one or more memory arrays and configured to cause the memory device to:
monitor a power level via the power management component;
determine that the power level varies from a range of power levels associated with the memory device based at least in part on monitoring the power level via the power management component, wherein one or more background operations are interrupted in response to the power level varying from the range of power levels, and wherein the one or more background operations comprise operations independent of an access command from a host;
transmit, by the power management component an indication that the power level varies from the range of power levels; and
resume the one or more background operations in accordance with information associated with the indication being restored.
9. The memory device of claim 8 , wherein the processing circuitry is further configured to cause the memory device to:
determine that the power level is below a threshold based at least in part on monitoring the power level, wherein determining that the power level varies from the range of power levels is based at least in part on the power level being below the threshold.
10. The memory device of claim 8 , wherein the processing circuitry is further configured to cause the memory device to:
detect that the power level associated with the memory device indicates a power loss at the memory device based at least in part on determining that the power level varies from the range of power levels.
11. The memory device of claim 8 , wherein the processing circuitry is further configured to cause the memory device to:
detect that the power level associated with the memory device indicates a power change at the memory device based at least in part on determining that the power level varies from the range of power levels.
12. The memory device of claim 8 , wherein the power level is associated with the one or more memory arrays.
13. The memory device of claim 8 , wherein the one or more memory arrays comprise volatile memory cells.
14. A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
monitor, by a power management component, a power level associated with the memory system;
determine, by the power management component, that the power level varies from one or more power levels associated with the memory system based at least in part on monitoring the power level, wherein one or more background operations are interrupted in response to the power level varying from the one or more power levels, and wherein the one or more background operations comprise operations independent of an access command from a host;
transmit, by the power management component, a signal indicating that the power level varies from the one or more power levels associated with the memory system; and
resume the one or more background operations based at least in part on information associated with the signal being restored.
15. The memory system of claim 14 , wherein the processing circuitry is further configured to cause the memory system to:
determine that the power level is below a threshold based at least in part on monitoring the power level, wherein determining that the power level varies from the one or more power levels is based at least in part on the power level being below the threshold.
16. The memory system of claim 14 , wherein, to transmit the signal, the processing circuitry is further configured to cause the memory system to:
transmit the signal indicating that the power level varies from the one or more power levels to a controller.
17. The memory system of claim 14 , wherein, to transmit the signal, the processing circuitry is further configured to cause the memory system to:
detect that the power level associated with the memory system indicates a power loss at the memory system based at least in part on determining that the power level varies from the one or more power levels.
18. The memory system of claim 14 , wherein, to transmit the signal, the processing circuitry is further configured to cause the memory system to:
detect that the power level associated with the memory system indicates a power change at the memory system based at least in part on determining that the power level varies from the one or more power levels.
19. The memory system of claim 14 , wherein the power level is associated with a memory medium of the memory system.
20. The memory system of claim 19 , wherein the memory medium comprises volatile memory cells.