Method of operating memory, memory, and memory system
According to one aspect, a method of operating a memory is provided. The method may include applying a first power supply voltage to a common source during a program precharge process. The method may include applying a first voltage to a first bottom gate line and applying a second voltage to a second bottom gate line starting at a first moment of the program precharge process. The method may include applying a second power supply voltage to the first bottom gate line and applying a third voltage to the second bottom gate line after the first moment of the program precharge process.
1 . A method of operating a memory, comprising:
applying a first power supply voltage to a common source during a program precharge process;
applying a first voltage to a first bottom gate line and applying a second voltage to a second bottom gate line starting at a first moment of the program precharge process, the first voltage being less than a first threshold voltage of a bottom select gate connected to the first bottom gate line, and the second voltage being greater than a second threshold voltage of a bottom select gate connected to the second bottom gate line; and
applying a second power supply voltage to the first bottom gate line and applying a third voltage to the second bottom gate line after the first moment of the program precharge process, the third voltage being less than a third threshold voltage of the bottom select gate connected to the second bottom gate line.
2 . The method of claim 1 , wherein the applying a second power supply voltage to the first bottom gate line and applying a third voltage to the second bottom gate line after the first moment of the program precharge process comprises:
applying the second power supply voltage to the first bottom gate line and applying the third voltage to a top-layer bottom gate line of the second bottom gate line starting at a second moment after the first moment of the program precharge process; and
applying the second power supply voltage to the first bottom gate line and the top-layer bottom gate line of the second bottom gate line and applying the third voltage to a bottom-layer bottom gate line of the second bottom gate line starting at a third moment after the second moment of the program precharge process.
3 . The method of claim 1 , further comprising:
applying a fourth voltage to the first bottom gate line before the first moment of the program precharge process, the fourth voltage being less than the second voltage and greater than a fourth threshold voltage of the bottom select gate connected to the first bottom gate line.
4 . The method of claim 1 , further comprising:
applying a bias voltage to selected word lines and applying the second power supply voltage to unselected word lines during the program precharge process.
5 . The method of claim 1 , further comprising:
applying a turn-on voltage to a selected top select gate and applying the second power supply voltage to an unselected top select gate during the program precharge process.
6 . The method of claim 1 , further comprising:
applying a first program voltage and a second program voltage to the first bottom gate line before the program precharge process,
wherein when applying the first program voltage:
a first bottom select gate of a first memory cell string and a first bottom select gate of a second memory cell string connected to the first bottom gate line are programmed to the first threshold voltage, and
wherein when applying the second program voltage:
the first bottom select gate of the second memory cell string is programmed to a fourth threshold voltage, the first threshold voltage being less than the fourth threshold voltage.
7 . The method of claim 6 , further comprising:
applying the first program voltage and the second program voltage to the second bottom gate line,
wherein when applying the first program voltage:
a second bottom select gate of the first memory cell string and a second bottom select gate of the second memory cell string connected to the second bottom gate line are programmed to the third threshold voltage, and
wherein when applying the second program voltage:
the second bottom select gate of the first memory cell string is programmed to the second threshold voltage, the third threshold voltage being less than the second threshold voltage.
8 . The method of claim 7 , wherein the first memory cell string and the second memory cell string are located in different fingers.
9 . A memory, comprising:
a plurality of memory cell strings, comprising:
a plurality of bottom select gates connected in series, a first bottom select gate of a first memory cell string and a first bottom select gate of a second memory cell string being connected to a first bottom gate line, a second bottom select gate of the first memory cell string and a second bottom select gate of the second memory cell string being connected to a second bottom gate line, and the second bottom select gate being located between the first bottom select gate and a common source; and
a peripheral circuit configured to:
apply a first power supply voltage to the common source during a program precharge process;
apply a first voltage to the first bottom gate line and apply a second voltage to the second bottom gate line starting at a first moment of the program precharge process, the first voltage being less than a first threshold voltage of the bottom select gate connected to the first bottom gate line, and the second voltage being greater than a second threshold voltage of the bottom select gate connected to the second bottom gate line; and
apply a second power supply voltage to the first bottom gate line and apply a third voltage to the second bottom gate line after the first moment of the program precharge process, the third voltage being less than a third threshold voltage of the bottom select gate connected to the second bottom gate line.
10 . The memory of claim 9 , wherein:
the second bottom gate line comprises a top-layer bottom gate line and a bottom-layer bottom gate line, and
the peripheral circuit is further configured to:
apply the second power supply voltage to the first bottom gate line and apply the third voltage to the top-layer bottom gate line of the second bottom gate line starting at a second moment after the first moment of the program precharge process; and
apply the second power supply voltage to the first bottom gate line and the top-layer bottom gate line of the second bottom gate line and apply the third voltage to the bottom-layer bottom gate line of the second bottom gate line starting at a third moment after the second moment of the program precharge process.
11 . The memory of claim 9 , wherein the peripheral circuit is further configured to:
apply a fourth voltage to the first bottom gate line before the first moment of the program precharge process, the fourth voltage being less than the second voltage and greater than a fourth threshold voltage of the bottom select gate connected to the first bottom gate line.
12 . The memory of claim 9 , wherein the peripheral circuit is further configured to:
apply a bias voltage to selected word lines and apply the second power supply voltage to unselected word lines during the program precharge process.
13 . The memory of claim 9 , wherein the peripheral circuit is further configured to:
apply a turn-on voltage to a selected top select gate and apply the second power supply voltage to an unselected top select gate during the program precharge process.
14 . The memory of claim 9 , wherein the peripheral circuit is further configured to:
apply a first program voltage and a second program voltage to the first bottom gate line before the program precharge process,
wherein when applying the first program voltage:
the first bottom select gate of the first memory cell string and the first bottom select gate of the second memory cell string connected to the first bottom gate line are programmed to the first threshold voltage, and
wherein when applying the second program voltage:
the first bottom select gate of the second memory cell string is programmed to a fourth threshold voltage, the first threshold voltage being less than the fourth threshold voltage.
15 . The memory of claim 14 , wherein the peripheral circuit is further configured to:
apply the first program voltage and the second program voltage to the second bottom gate line,
wherein when applying the first program voltage:
the second bottom select gate of the first memory cell string and the second bottom select gate of the second memory cell string connected to the second bottom gate line are programmed to the third threshold voltage, and
wherein when applying the second program voltage:
the second bottom select gate of the first memory cell string is programmed to the second threshold voltage, the third threshold voltage being less than the second threshold voltage.
16 . The memory of claim 15 , wherein the first memory cell string and the second memory cell string are located in different fingers.
17 . A memory system, comprising:
one or more memories, each comprising:
a plurality of memory cell strings, comprising:
a plurality of bottom select gates connected in series, a first bottom select gate of a first memory cell string and a first bottom select gate of a second memory cell string being connected to a first bottom gate line, a second bottom select gate of the first memory cell string and a second bottom select gate of the second memory cell string being connected to a second bottom gate line, and the second bottom select gate being located between the first bottom select gate and a common source; and
a peripheral circuit configured to:
apply a first power supply voltage to the common source during a program precharge process;
apply a first voltage to the first bottom gate line and apply a second voltage to the second bottom gate line starting at a first moment of the program precharge process, the first voltage being less than a first threshold voltage of the bottom select gate connected to the first bottom gate line, and the second voltage being greater than a second threshold voltage of the bottom select gate connected to the second bottom gate line; and
apply a second power supply voltage to the first bottom gate line and apply a third voltage to the second bottom gate line after the first moment of the program precharge process, the third voltage being less than a third threshold voltage of the bottom select gate connected to the second bottom gate line; and
a memory controller coupled to the memories and configured to control the memories.