Chiplet communication using an optical communication substrate
Described herein are a computing systems comprising a photonic interposer having an optical network comprising a plurality of waveguides and a plurality of controllable optical switches; an electronic die having a surface bonded to the photonic interposer, an inner interface comprising a first plurality of ports electrically coupling the electronic die to the photonic interposer through the surface; and an outer interface comprising a second plurality of ports electrically coupling the electronic die to the photonic interposer through the surface, wherein the outer interface at least partially encloses the inner interface.
1. A method for manufacturing a computing system, comprising:
obtaining a photonic interposer having an optical network comprising a plurality of optical switches including at least a first optical switch and a second optical switch and one or more waveguides optically coupling the first optical switch to the second optical switch;
bonding a first electronic die to the photonic interposer through a first surface of the first electronic die, wherein bonding the first electronic die comprises connecting the first electronic die to the photonic interposer through a first interface comprising a first two-dimensional array of ports arranged in at least three columns and at least three rows, wherein the first interface comprises:
a first inner interface comprising a first plurality of ports of the first two-dimensional array of ports electrically coupling the first electronic die to the photonic interposer through the first surface; and
a first outer interface comprising a second plurality of ports of the first two-dimensional array of ports electrically coupling the first electronic die to the photonic interposer through the first surface, wherein the first outer interface at least partially encloses the first inner interface,
wherein the first electronic die, when bonded to the photonic interposer, is associated with the first optical switch such that the first optical switch is configured to selectively couple the first electronic die to the one or more optical waveguides; and
bonding a second electronic die to the photonic interposer through a second surface of the second electronic die, wherein bonding the second electronic die comprises connecting the second electronic die to the photonic interposer through a second interface comprising a second two-dimensional array of ports arranged in at least three columns and at least three rows, wherein the second interface comprises:
a second inner interface comprising a third plurality of ports of the second two-dimensional array of ports electrically coupling the second electronic die to the photonic interposer through the second surface; and
a second outer interface comprising a fourth plurality of ports of the second two-dimensional array of ports electrically coupling the second electronic die to the photonic interposer through the second surface, wherein the second outer interface at least partially encloses the second inner interface,
wherein the second electronic die, when bonded to the photonic interposer, is associated with the second optical switch such that the second optical switch is configured to selectively couple the second electronic die to the one or more optical waveguides.
2. The method of claim 1 , wherein at least one port of the first outer interface is positioned within 1 mm of an outer perimeter of the first electronic die.
3. The method of claim 2 , wherein at least one port of the first inner interface is positioned more than 1 mm away from the outer perimeter of the first electronic die.
4. The method of claim 3 , wherein the first surface of the first electronic die is between 25 mm 2 and 625 mm 2 .
5. The method of claim 1 , wherein:
when the first electronic die is bonded to the photonic interposer, the first optical switch is disposed within a first area defined by the first electronic die, and
when the second electronic die is bonded to the photonic interposer, the second optical switch is disposed within a second area defined by the second electronic die.
6. A computing system comprising:
a photonic interposer having an optical network comprising a plurality of optical switches including at least a first optical switch and a second optical switch and one or more waveguides optically coupling the first optical switch to the second optical switch;
a first electronic die having a first surface bonded to the photonic interposer, wherein the first optical switch is associated with the first electronic die such that the first optical switch is configured to selectively couple the first electronic die to the one or more optical waveguides, the first electronic die having a first interface comprising a first two-dimensional array of ports arranged in at least three columns and at least three rows, wherein the first interface comprises:
a first inner interface comprising a first plurality of ports of the first two-dimensional array of ports electrically coupling the first electronic die to the photonic interposer; and
a first outer interface comprising a second plurality of ports of the first two-dimensional array of ports electrically coupling the first electronic die to the photonic interposer, wherein the first outer interface at least partially encloses the first inner interface; and
a second electronic die having a second surface bonded to the photonic interposer, wherein the second optical switch is associated with the second electronic die such that the second optical switch is configured to selectively couple the second electronic die to the one or more optical waveguides,
the second electronic die having a second interface comprising a second two-dimensional array of ports arranged in at least three columns and at least three rows, wherein the second interface comprises:
a second inner interface comprising a third plurality of ports of the second two-dimensional array of ports electrically coupling the second electronic die to the photonic interposer; and
a second outer interface comprising a fourth plurality of ports of the second two-dimensional array of ports electrically coupling the second electronic die to the photonic interposer, wherein the second outer interface at least partially encloses the second inner interface,
wherein the optical network optically couples at least one port of the first inner interface to at least one port of the second inner interface.
7. The computing system of claim 6 , wherein each port of the first and second pluralities of ports comprises:
an electric connection connecting the first electronic die to the interposer; and
a SerDes coupled to the electric connection.
8. The computing system of claim 7 , wherein the SerDes is formed on the first electronic die.
9. The computing system of claim 6 , wherein at least one port of the first outer interface is positioned within 1 mm of an outer perimeter of the first electronic die.
10. The computing system of claim 9 , wherein at least one port of the first inner interface is positioned more than 1 mm away from the outer perimeter of the first electronic die.
11. The computing system of claim 6 , wherein the inner interface spans at least 20% of the first surface of the first electronic die bonded to the photonic interposer.
12. The computing system of claim 6 , wherein the first optical switch is disposed within a first area defined by the first electronic die and wherein the second optical switch is disposed within a second area defined by the second electronic die.
13. The computing system of claim 7 , wherein the photonic interposer further comprises a transimpedance amplifier (TIA) and a modulator driver coupled to the optical network, wherein the SerDes couples to either the TIA, the modulator driver, or both.
14. The computing system of claim 6 , wherein the first surface of the first electronic die is between 25 mm 2 and 625 mm 2 .
15. The computing system of claim 6 , wherein the photonic interposer further comprises an off-chip optical coupler, wherein the photonic network couples the off-chip optical coupler to at least one port of the first inner interface.
16. The computing system of claim 6 , wherein each port of the first and second pluralities of ports comprises an Advanced Interface Bus (AIB) interface or a Universal Chiplet Interconnect Express (UCIe) interface.