Photonic communication platform and related architectures, systems and methods
Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.
1. A photonic interposer comprising:
a plurality of photonics tiles that are instantiations of a template photonic tile, each of the plurality of photonics tiles comprising:
a transceiver comprising a transmitter and a receiver;
electrical connections, coupled to the transceiver, configured to permit electrical communication between the transceiver and an electronic chip when the electronic chip is attached to the photonic interposer in correspondence with the photonic tile;
an optical distribution network comprising a first set of bus waveguides optically coupled to the transceiver, a second set of bus waveguides, and a plurality of programmable interconnections, each programmable interconnection being configured to selectively place a bus waveguide of the first set of bus waveguides in optical communication with a bus waveguide of the second set of bus waveguides, wherein each programmable interconnection comprises a waveguide crossing and an active coupler.
2. The photonic interposer of claim 1 , wherein the transceiver comprises:
a plurality of modulators, coupled to a first bus waveguide of the first set of bus waveguides, tuned at different wavelengths relative to one another; and
a plurality of drop filters, coupled to a second bus waveguide of the first set of bus waveguides, tuned at different wavelengths relative to one another.
3. The photonic interposer of claim 2 , wherein the plurality of modulators are resonant modulators, and the plurality of drop filters are resonant drop filters.
4. The photonic interposer of claim 1 , wherein the transmitter is configured to transmit data along a first bus waveguide of the first set of bus waveguides either in a first direction or a second direction.
5. The photonic interposer of claim 4 , wherein each of the plurality of photonics tiles further comprises a 2×2 coupler coupling the transceiver to the first bus waveguide of the first set of bus waveguides.
6. The photonic interposer of claim 5 , wherein the 2×2 coupler comprises first, second, third and fourth terminals, wherein:
the first terminal is coupled to an output of the transmitter,
the second terminal is coupled to an input of the receiver, and
the third and fourth terminals are coupled to the first bus waveguide of the first set of bus waveguides.
7. The photonic interposer of claim 4 , wherein each of the plurality of photonics tiles further comprises an interferometer having an input and first and second outputs, and a resonant filter, wherein:
the transmitter is coupled to the input of the interferometer, and
the first and second outputs of the interferometer are coupled to the resonant filter, and
the resonant filter is coupled to the first bus waveguide of the first set of bus waveguides.
8. The photonic interposer of claim 4 , wherein each of the plurality of photonics tiles further comprises an interferometer having an output and first and second inputs, and a resonant filter, wherein:
the resonant filter is coupled to the first bus waveguide of the first set of bus waveguides,
the first and second inputs of the interferometer are coupled to the resonant filter, and
the receiver is coupled to the output of the interferometer.
9. The photonic interposer of claim 1 , wherein the waveguide crossing comprises a first waveguide patterned in a first waveguide layer, a second waveguide patterned in a second waveguide layer, and a third waveguide layer patterned in a third waveguide layer, wherein:
the second waveguide layer is between the first and third waveguide layers, and
the first waveguide is evanescently coupled with the second waveguide and the second waveguide is evanescently coupled with the third waveguide.
10. The photonic interposer of claim 9 , wherein the first waveguide layer is made of silicon, and both the second and the third waveguide layers are made of silicon nitride.
11. The photonic interposer of claim 1 , wherein the active coupler comprises a first terminal coupled to a first additional active coupler, a second terminal coupled to a first additional active coupler, and a third terminal coupled to the waveguide crossing.
12. The photonic interposer of claim 11 , wherein the active coupler comprises first and second Mach Zehnder interferometers (MZI), wherein the first terminal corresponds to a first output of the first MZI, the second terminal corresponds to a second output of the first MZI, and the third terminal corresponds to an output of the second MZI.
13. The photonic interposer of claim 1 , wherein the bus waveguides of the second set of bus waveguides traverse multiple photonic tiles.
14. The photonic interposer of claim 1 , wherein each of the plurality of photonics tiles further comprises:
a polarization splitter coupled to both the transmitter and the receiver; and
a fiber coupler coupled to the polarization splitter.
15. The photonic interposer of claim 1 , wherein the plurality of photonics tiles are arranged two-dimensionally and form a plurality of columns of photonic tiles and a plurality of rows of photonic tiles.
16. The photonic interposer of claim 1 , wherein each of the plurality of photonics tiles is 24.8 mm×32 mm in size.
17. A computing system comprising the photonic interposer of claim 1 and a first application-specific integrated circuit (ASIC) mounted on the photonic interposer, wherein the first ASIC comprises a first serializer-deserializer (SerDes) coupled to a first transmitter of the photonic interposer and a second SerDes coupled to a first receiver of the photonic interposer.
18. The computing system of claim 17 , further comprising a plurality of through silicon vias (TSV) coupling the first SerDes with the first transmitter.
19. The computing system of claim 17 , wherein the first ASIC comprises a Universal Chiplet Interconnect Express (UCIe) interface coupled to the first SerDes and configured to permit communication between the first ASIC and a second ASIC.
20. The computing system of claim 17 , wherein the second ASIC is mounted on the photonic interposer.