Selective single-level memory cell operation
A method includes selectively configuring a first subset of non-volatile memory blocks to operate in a single-level mode, configuring the first subset of non-volatile memory blocks to collectively operate as a pseudo single-level cache, writing data associated with performance of a memory operation to the first subset of non-volatile memory blocks, and migrating the data from the first subset of non-volatile memory blocks to a second subset of non-volatile memory blocks.
1. A method comprising:
configuring a first subset of non-volatile memory blocks of a non-volatile memory to collectively operate as a pseudo single-level cache responsive to detection of a backup power supply failure event;
writing data associated with a memory operation to the first subset of non-volatile memory blocks configured as the pseudo single-level cache; and
migrate the data from the first subset to a second subset of non-volatile memory blocks of the non-volatile memory.
2. The method of claim 1 , further comprising selectively configuring the first subset of non-volatile memory blocks to operate in a single-level mode responsive to detection of an asynchronous power loss (APL) event.
3. The method of claim 2 , further comprising selectively configuring free non-volatile memory blocks to operate in the single-level mode.
4. The method of claim 3 , further comprising:
maintaining a quantity of blocks in a free block pool that is equal to or greater than a target quantity of blocks; and
selectively configuring, from the free block pool, the free non-volatile memory blocks to operate in the single-level mode until a quantity of blocks in the first subset of non-volatile memory blocks is equal to the target quantity of blocks.
5. The method of claim 1 , further comprising determining a target quantity block in the first subset of non-volatile memory blocks based on an expected operational lifetime of the first subset of non-volatile memory blocks, the second subset of non-volatile memory blocks, or both.
6. The method of claim 1 , further comprising determining, based on comparison of an expected operational lifetime of the second subset of non-volatile memory blocks, a target quantity of the first subset of non-volatile memory blocks.
7. The method of claim 1 , further comprising designating, based on an expected operation lifetime of the first subset of non-volatile memory blocks being equal to an expected operational lifetime of the second subset of non-volatile memory blocks, a target quantity of the first subset of non-volatile memory blocks.
8. The method of claim 2 , wherein selectively configuring the first subset of non-volatile memory blocks to operate in the single-level mode further comprises generating a target quantity of the first subset of non-volatile memory blocks subsequent to detection of the backup power supply failure event.
9. The method of claim 1 , further comprising writing data, associated with performance of a plurality of memory operations, to sequential blocks of non-volatile memory included in the first subset of non-volatile memory blocks.
10. An apparatus, comprising:
a volatile memory;
a non-volatile memory comprising non-volatile memory blocks; and
a controller configured to:
responsive to detection of a backup power supply failure event, selectively configure a first subset of non-volatile memory blocks of the non-volatile memory to operate in a single-level mode; and
in response to receipt of signaling indicative of an access request from a host:
write data associated with a memory operation to the volatile memory;
write the data from the volatile memory to the first subset of non-volatile memory blocks; and
migrate the data from the first subset of non-volatile memory blocks to a second subset of non-volatile memory blocks of the non-volatile memory.
11. The apparatus of claim 10 , wherein the controller is further configured to responsive to detection of the backup power supply failure event, selectively configure the first subset of non-volatile memory blocks to operate as a pseudo single-level cache.
12. The apparatus of claim 11 , wherein the controller is to configure the first subset of non-volatile memory blocks to a multi-level mode in an absence of a detection of the backup power supply failure event.
13. The apparatus of claim 10 , wherein the first subset of the non-volatile memory blocks has a respective block size that is less than a respective block size of the second subset of non-volatile memory blocks.
14. The apparatus of claim 10 , wherein the first subset of non-volatile memory blocks have a page size that is less than a page size of the second subset of non-volatile memory blocks.
15. The apparatus of claim 10 , wherein a sum of a first quantity of the first subset of non-volatile memory blocks and a second quantity of the second subset of non-volatile memory blocks is equal to a total block count of the non-volatile memory.
16. A system comprising:
a volatile memory; and
a non-volatile memory; and
a processing device to perform operations comprising:
operate the volatile memory in accordance with a write-back cache policy;
configure a first portion of the non-volatile memory to operate in a single-level mode as a pseudo single-level cache responsive to detection of a backup power supply failure event;
write data from the volatile memory to the first portion of the non-volatile memory configured to operate as the pseudo single-level cache; and
responsive to a threshold amount of data being written to the first portion of the non-volatile memory, internally migrate the data from the first portion of the non-volatile memory to a second portion of the non-volatile memory.
17. The system of claim 16 , wherein blocks in the first portion of the non-volatile memory are configured to operate collectively as the pseudo single-level cache by being assigned consecutive block index numbers.
18. The system of claim 16 , wherein the non-volatile memory is comprised of multi-level cells, triple level cells, quad-level cells, or penta-level cells.
19. The system of claim 16 , wherein the threshold amount of data is equal to a page size of a page included in a non-volatile memory block in the second portion of the non-volatile memory.
20. The system of claim 16 , wherein the processing device is further to operate the volatile memory in accordance with a write-through cache policy responsive to a detection of the backup power supply failure event.