Semiconductor memory structure with support frame in staircase region and method of making the same
A semiconductor structure and method of manufacturing are disclosed. The semiconductor structure includes: a substrate having an adjacent array area and a peripheral region; a bit line extending along a first direction, a semiconductor channel extending along a second direction and a word line extending along a third direction located on the array area; the ladder structure in the periphery region includes a plurality of steps each is in contact with either the bit line or the word line; a plurality of conductive columns in contact with the top surfaces of the steps and extending along the direction that is the same direction as the other one of the bit line or the word line; and a support frame located between any two adjacent conductive columns and connected to each step of the ladder structure.
1 . A semiconductor structure, comprising:
a substrate, wherein the substrate comprises an array region located adjacently, and a peripheral region;
a bit line extending along a first direction, a semiconductor channel extending along a second direction and a word line extending along a third direction, wherein the bit line, the semiconductor channel and the word line are all located in the array region, wherein two of the first direction, the second direction and the third direction intersect each other;
a ladder structure located in the peripheral region, wherein the ladder structure comprises a plurality of steps, wherein each of the plurality of steps is contact-connected to one of the bit line and the word line;
a plurality of conductive columns, wherein each of the plurality of conductive columns is connected to a top surface of one of the plurality of steps, wherein an extending direction of the plurality of conductive columns is a same as the extending direction of another of the bit line and the word line; and
a support frame, wherein the support frame is located between two adjacent ones of the plurality of conductive columns, and wherein the support frame is in contact with each of the plurality of steps;
wherein, along the extending direction of the plurality of conductive columns, a height of the top surface of one of the plurality of steps is different from a top surface of another one of the plurality of steps, and wherein two adjacent ones of the plurality of steps are electrically insulated;
wherein the plurality of steps is arranged in an array in a plane of the first direction and the second direction;
wherein, along the direction in which the array region points to the peripheral region, top surface heights of ones of the plurality of steps arranged at intervals along the first direction gradually decrease, and top surface heights of ones of the plurality of steps arranged at intervals along the second direction also gradually decrease.
2 . The semiconductor structure according to claim 1 , further comprising, along the extension direction of the plurality of conductive columns, a first top surface, which is a top surface of the support frame away from the substrate, a second top surface, which is a top surface of a step in the plurality of steps farthest from the substrate, wherein the first top surface is not lower than the second top surface, wherein a bottom surface of the support frame close to the substrate is a first bottom surface, and a bottom surface of one of the plurality of steps closest to the substrate is a second bottom surface, and wherein the first bottom surface is not higher than the second bottom surface.
3 . The semiconductor structure according to claim 1 , wherein the support frame comprises support layers, wherein each of the support layers and at least two of the plurality of steps are in contact connection, and wherein the plurality of steps is respectively located on opposite sides of each of the support layers along the first direction and/or on opposite sides of each of the support layers in the second direction.
4 . The semiconductor structure according to claim 3 , wherein one of the plurality of steps is contact-connected to the bit line in an one-to-one correspondence; wherein the support frame comprises: a first support layer arranged at intervals and extending in one of the first direction and the second directions, and a second support layer arranged at intervals along another one of the first direction (and the second direction, and wherein, the second support layer is located in an interval between two adjacent first support layers.
5 . The semiconductor structure according to claim 4 , wherein the extension direction of the first support layer is a reference direction, wherein the plurality of steps arranged at intervals along the reference direction is all contact-connected with the first support layer.
6 . The semiconductor structure according to claim 4 , wherein the extension direction of the first support layer is a reference direction, wherein multiples of the first support layers are arranged at intervals along the reference direction, wherein multiples of the plurality of steps arranged at intervals along the reference direction are in contact with multiples of the plurality of first support layers respectively.
7 . The semiconductor structure according to claim 3 , wherein one of the plurality of steps is contact connected to the bit lines in an one-to-one correspondence; wherein the support frame comprises: the first support layer, extending along the first direction and the second direction, and the second support layer, located in an interval between two adjacent first support layers;
wherein, the first support layer is in contact with four steps of the plurality of steps arranged in an array, and wherein the first support layer is arranged at intervals along the first direction and/or the second direction, and wherein the second support layer is arranged in contact connection with four steps of the plurality of steps arranged in an array.
8 . The semiconductor structure according to claim 1 , wherein the support frame is a grid-like structure, wherein the grid-like structure comprises a plurality of spaces, wherein the plurality of steps is located in the plurality of spaces corresponding to the plurality of spaces in an one by one correspondence.
9 . The semiconductor structure according to claim 1 , wherein a material of the support frame comprises at least one of silicon nitride or silicon oxynitride.
10 . The semiconductor structure according to claim 1 , wherein the peripheral region comprises a spacer region between the ladder structure and the array region, wherein the bit line or the word line is also located in the spacer region; and
wherein the semiconductor structure further comprises: a peripheral protection layer, wherein the peripheral protection layer is located in the spacer region and surrounds a sidewall of the bit line or a sidewall of the word line extending along the first direction in the spacer region.
11 . The semiconductor structure according to claim 10 , wherein the peripheral protective layer surrounds a sidewall of the ladder structure extending along the extending direction of the conductive columns, and wherein an interval is located between part of the peripheral protective layer and the ladder structure.
12 . The semiconductor structure according to claim 10 , wherein a material of the peripheral protective layer is a same as a material of the support frame.
13 . A method of fabricating a semiconductor structure, comprising:
providing a substrate having an adjacent array region and a peripheral region;
forming bit lines in the array region extending along a first direction, semiconductor channels extending along a second direction, and word lines extending along a third direction, wherein two of the first direction, the second direction and the third direction intersect each other; and
forming a ladder structure, conductive columns and a support frame in the peripheral region, wherein the ladder structure comprises a plurality of steps, wherein the plurality of steps is in one-to-one contact connection with one of the bit lines and the word line; wherein each of the conductive columns is in one-to-one contact connection with each of the plurality of steps, and wherein the conductive columns extends in a same direction as another one of the bit lines and the word line;
wherein the support frame is located on any adjacent two conductive columns, and is in contact with each of the plurality of steps;
wherein along the extension direction of the conductive columns, a height of a top surface of one of the plurality of steps is different from a height of a top surface of another one of the plurality of steps, and wherein adjacent ones of the plurality of steps are electrically insulated from each other;
wherein forming the ladder structure comprises:
forming an initial stack structure having multi-layers arranged along the extension direction of the conductive columns in the peripheral region, wherein along the extension direction of the conductive columns, the initial stack structure comprises a first semiconductor layer and a second semiconductor layer stacked together, wherein the initial stack structure has a pitch region close to the array region and a step region located at on a side of the pitch region away from the array region;
performing a first patterning process on the initial stacked structure of the step region to form initial ladder structures, wherein the initial ladder structures comprise a plurality of initial step structures, wherein along the extending direction of the conductive columns a height of a top surface of one of the initial step structures is different from a height of a top surface of another initial step structure; and
etching an initial ladder structure to form spaces in which the plurality of steps are formed.
14 . The manufacturing method according to claim 13 , wherein, after forming the initial ladder structure, before etching the initial ladder structure to form the plurality of steps, forming the support frame comprises:
forming a first dielectric layer, wherein the first dielectric layer is located on a top surface of each of the initial step structures, wherein the initial step structure farthest from the substrate is a reference top surface, and wherein a top surface of the first dielectric layer away from the substrate is flush with the reference top surface; and
performing a second patterning process on the initial ladder structure and the first dielectric layer to form a first groove; and
forming the support frame to fill the first groove.
15 . The manufacturing method according to claim 14 , wherein the first dielectric layer is also located on opposite sides of the initial ladder structure along the second direction;
after forming the initial ladder structure, before etching the initial ladder structure, forming the plurality of steps further comprising:
performing a third patterning process on the initial stack structure and the first dielectric layer of the spacing region, to form a second groove; and
forming a peripheral protective layer to fill the second groove.
16 . The manufacturing method according to claim 15 , wherein, after forming the peripheral protection layer, said etching the initial ladder structure to form a spacer comprises:
removing the first dielectric layer between the initial ladder structure and the peripheral protective layer, to expose the initial ladder structure along the second direction on opposite sides;
etching the second semiconductor layer in the initial ladder structure along the second direction to form the spacer; and
forming the plurality of steps to fill the spacer.
17 . The manufacturing method according to claim 16 , wherein, after forming the plurality of steps, further comprising:
etching the first semiconductor layer in the initial ladder structure along the second direction to form a gap; and
forming a second dielectric layer, wherein the second dielectric layer fills the gap, and a space between the peripheral protective layer and the ladder structure.