IP Library Granted Patent US 12,727,400
Granted Patent B2
US 12,727,400 · App. 18/563,408 · Granted Sep 1, 2026

Silicon carbide epitaxial substrate and method of manufacturing silicon carbide semiconductor device

Inventors: Hiroki Nishihara (Osaka, JP); Tsubasa Honke (Osaka, JP); Takaya Miyase (Osaka, JP); Taro Enokizono (Osaka, JP)
Assignee: Sumitomo Electric Industries, Ltd.
H10P14/2904H10P14/3408H10P36/00
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Quick Facts
Patent No.
US 12,727,400
App. No.
18/563,408
Granted
Sep 1, 2026
Kind
B2
Abstract

A silicon carbide epitaxial substrate includes a silicon carbide substrate and a silicon carbide epitaxial layer. A plurality of square regions are constituted of a plurality of outer peripheral regions located at an outermost periphery of the plurality of square regions and a plurality of central regions surrounded by the plurality of outer peripheral regions. When a maximum value of LTIR of the silicon carbide epitaxial substrate in the plurality of outer peripheral regions is defined as a first value and a maximum value of LTIR of the silicon carbide epitaxial substrate in the plurality of central regions is defined as a second value, a value obtained by dividing the first value by the second value is 0.8 to 1.2. An area density of a pit in a second main surface is 0.5/cm 2 or less.

Claims (35)

1 . A silicon carbide epitaxial substrate comprising:

a silicon carbide substrate; and

a silicon carbide epitaxial layer on the silicon carbide substrate,

wherein the silicon carbide substrate has a first main surface located opposite to an interface between the silicon carbide substrate and the silicon carbide epitaxial layer,

the silicon carbide epitaxial layer has a second main surface located opposite to the interface,

when the second main surface is divided into a plurality of square regions each having each side having a length of 10 mm, the plurality of square regions are constituted of a plurality of outer peripheral regions located at an outermost periphery of the plurality of square regions and a plurality of central regions surrounded by the plurality of outer peripheral regions,

when a maximum value of local total indicated reading (LTIR) of the silicon carbide epitaxial substrate in the plurality of outer peripheral regions is defined as a first value and a maximum value of local total indicated reading (LTIR) of the silicon carbide epitaxial substrate in the plurality of central regions is defined as a second value, a value obtained by dividing the first value by the second value is 0.8 to 1.2,

an area density of a pit in the second main surface is 0.5/cm 2 or less,

an area of the pit is 100 μm 2 or less when viewed in a direction perpendicular to the second main surface, and

a depth of the pit is 0.01 μm to 0.1 μm in the direction perpendicular to the second main surface.

2 . A silicon carbide epitaxial substrate comprising:

a silicon carbide substrate; and

a silicon carbide epitaxial layer on the silicon carbide substrate,

wherein the silicon carbide substrate has a first main surface located opposite to an interface between the silicon carbide substrate and the silicon carbide epitaxial layer,

the silicon carbide epitaxial layer has a second main surface located opposite to the interface,

when the second main surface is divided into a plurality of square regions each having each side having a length of 10 mm, the plurality of square regions are constituted of a plurality of outer peripheral regions located at an outermost periphery of the plurality of square regions and a plurality of central regions surrounded by the plurality of outer peripheral regions,

when a maximum value of local total indicated reading (LTIR) of the silicon carbide epitaxial substrate in the plurality of outer peripheral regions is defined as a first value and a maximum value of local total indicated reading (LTIR) of the silicon carbide epitaxial substrate in the plurality of central regions is defined as a second value, a value obtained by dividing the first value by the second value is 0.8 to 1.2,

an area density of a bump in the second main surface is 0.5/cm 2 or less,

an area of the bump is 100 μm 2 or less when viewed in a direction perpendicular to the second main surface, and

a height of the bump is 0.01 μm to 0.1 μm in the direction perpendicular to the second main surface.

3 . The silicon carbide epitaxial substrate according to claim 1 ,

wherein an area density of a bump in the second main surface is 0.5/cm 2 or less,

an area of the bump is 100 μm 2 or less when viewed in the direction perpendicular to the second main surface, and

a height of the bump is 0.01 μm to 0.1 μm in the direction perpendicular to the second main surface.

4 . The silicon carbide epitaxial substrate according to claim 1 , wherein an area density of a three-dimensional oblique defect in the second main surface is 0.006/cm 2 to 0.2/cm 2 .

5 . The silicon carbide epitaxial substrate according to claim 1 , wherein the second main surface has a diameter of 100 mm or more.

6 . The silicon carbide epitaxial substrate according to claim 1 ,

wherein an off-angle of the second main surface relative to a {0001} plane is 5° or less.

7 . The silicon carbide epitaxial substrate according to claim 1 , wherein a polytype of silicon carbide forming each of the silicon carbide substrate and the silicon carbide epitaxial layer is 4H.

8 . The silicon carbide epitaxial substrate according to claim 1 ,

wherein the silicon carbide epitaxial layer includes an n-type impurity, and

the n-type impurity has a concentration of 1×10 15 cm −3 to 1×10 19 cm −3 .

9 . A method of manufacturing a silicon carbide semiconductor device, the method comprising:

preparing the silicon carbide epitaxial substrate according to claim 1 ; and

processing the silicon carbide epitaxial substrate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2026
From: SUMITOMO ELECTRIC INDUSTRIES, LTD.
To: MITSUMI ELECTRIC CO., LTD.
Reel/Frame 074860/0548 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2023
From: NISHIHARA, HIROKI; HONKE, TSUBASA; MIYASE, TAKAYA; ENOKIZONO, TARO
To: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Reel/Frame 065642/0769 →
Priority Claims (1)
JP 2021-087625 · May 25, 2021 · national
Continuity (1)
Related Publication 20240274434A1 · Aug 15, 2024
References Cited (4)
JP 201759670A · 2017 [cited by applicant]
JP 201776650A · 2017 [cited by applicant]
JP 2020125241A · 2020 [cited by applicant]
L. Scaltrito et al., “Defect influence on the electrical properties of 4H-SiC Schottky diodes”, Materials Science Forum vols. 457-460, pp. 1081-1084, 2004. [cited by applicant]