Stateful logic-in-memory using silicon diodes
View Patent ↗Disclosed is a stateful logic-in-memory using silicon diodes. More particularly, the stateful logic-in-memory according to an embodiment of the present invention includes a plurality of silicon diodes, each of the silicon diodes includes an anode region, a first channel region, a second channel region and a cathode region and is included as a memory cell.
1 . A stateful logic-in-memory using silicon diodes, wherein the stateful logic-in-memory comprises a plurality of silicon diodes respectively comprising an anode region, a first channel region, a second channel region and a cathode region and being respectively comprised as memory cells,
wherein each of the plural memory cells is connected in series with a resistor after a terminal of the cathode region is connected in parallel with a terminal of another cathode region, and receives operation voltage through a terminal of the anode region, and
the plural memory cells comprise at least one input cell and output cell, perform implication (IMP) calculation at least once based on the received operation voltage and states of the at least one input cell and output cell, and change or maintain the state of the output cell based on the IMP operation performed at least once to perform a logic operation function and a memory function.
2 . The stateful logic-in-memory according to claim 1 , wherein the at least one input cell receives one voltage of a set voltage, a hold voltage and a read voltage among the operation voltage, wherein, when the set voltage is a positive voltage, a state is determined as a high state, thereby being turned on, and, when the set voltage is a negative voltage, a state is determined as a low state, thereby being turned off, and
the output cell receives one voltage of a set voltage, a hold voltage and a write voltage among the operation voltage, wherein, when the set voltage is a positive voltage, a state is determined as a high state, thereby being turned on, and, when the set voltage is a negative voltage, a state is determined as a low state, thereby being turned off, wherein the state is maintained or changed based on the write voltage.
3 . The stateful logic-in-memory according to claim 2 , wherein the plural memory cells are turned on based on a latch-up phenomenon in the first channel region and the second channel region when the set voltage is the positive voltage corresponding to a greater voltage than a reference voltage for generating a positive feedback loop in the first channel region and the second channel region, and are turned off based on a latch-down phenomenon in the first channel region and the second channel region when the set voltage is the negative voltage corresponding to a smaller voltage than the reference voltage.
4 . The stateful logic-in-memory according to claim 2 , wherein the stateful logic-in-memory comprises one input cell of the at least one input cell and the output cell, and
the stateful logic-in-memory has a larger resistance value than the resistor connected in series as the one input cell is turned off when the one input cell is in a low state and the output cell is in a low state or a high state, and performs an IMP operation, where the output cell is changed from a low state to a high state or maintains a high state, based on the write voltage applied to the output cell because the read voltage applied to the input cell is not applied to the resistor based on the larger resistance value.
5 . The stateful logic-in-memory according to claim 2 , wherein the stateful logic-in-memory comprises one input cell of the at least one input cell and the output cell, and
the stateful logic-in-memory has a smaller resistance value than the resistor connected in series as the one input cell is turned on when the one input cell is in a high state and the output cell is in a low state or a high state, and performs an IMP operation, where the output cell maintains a previous low state or high state, as the write voltage and read voltage applied to the output cell are canceled out while the read voltage applied to the input cell is applied to the resistor based on the smaller resistance value.
6 . The stateful logic-in-memory according to claim 2 , wherein the stateful logic-in-memory comprises one input cell of the at least one input cell and the output cell,
the output cell receives the set voltage as a negative voltage, thereby being reset to a low state, and
the stateful logic-in-memory has a larger resistance value than the resistor connected in series as the one input cell is turned off when the one input cell is in a low state and the output cell is in a low state, and performs an IMP operation, where the output cell is changed from a low state to a high state, based on the write voltage applied to the output cell because the read voltage applied to the input cell is not applied to the resistor based on the larger resistance value.
7 . The stateful logic-in-memory according to claim 6 , wherein the stateful logic-in-memory has a smaller resistance value than the resistor connected in series as the one input cell is turned on when the one input cell is in a high state and the output cell is in a low state, and performs an IMP operation, where the output cell maintains a previous low state, as the write voltage and read voltage applied to the output cell are canceled out while the read voltage applied to the input cell is applied to the resistor based on the smaller resistance value.
8 . The stateful logic-in-memory according to claim 2 , wherein the stateful logic-in-memory comprises two input cells of the at least one input cell and the output cell,
the output cell receives the set voltage as a negative voltage, thereby being reset to a low state,
the stateful logic-in-memory performs a first IMP operation between one input cell of the two input cells and the output cell,
the stateful logic-in-memory performs a second IMP operation between another input cell of the two input cells and the output cell, and
the stateful logic-in-memory stores a NAND operation result value between the one input cell and the another input cell in the output cell based on the first IMP operation and the second IMP operation.
9 . The stateful logic-in-memory according to claim 2 , wherein the stateful logic-in-memory comprises two input cells of the at least one input cell and the output cell,
the output cell receives the set voltage as a negative voltage, thereby being reset to a low state,
the read voltage is applied to the two input cells, and IMP operation between an OR operation result of a state of the two input cells and the output cell is performed, and
the stateful logic-in-memory stores a NOR operation result value between the one input cell and the another input cell, based on the IMP operation, in the output cell.
10 . The stateful logic-in-memory according to claim 2 , wherein the stateful logic-in-memory comprises first to fourth input cells of the at least one input cell and the output cell,
the third and fourth input cells of the first to fourth input cells and the output cell receive the set voltage as a negative voltage, thereby being reset to a low state,
the stateful logic-in-memory performs IMP operation between the first input cell and the third input cell to store a first operation result as a state of the third input cell,
the stateful logic-in-memory performs IMP operation between the second input cell and the fourth input cell to store a second operation result as a state of the fourth input cell,
the stateful logic-in-memory performs IMP operation between an OR operation result of the first input cell and the second operation result and the output cell to store a third operation result as a state of the output cell, and
the stateful logic-in-memory performs IMP operation between an OR operation result of the second input cell and the first operation result and the output cell to store a fourth operation result as a state of the output cell.
11 . The stateful logic-in-memory according to claim 1 , wherein the anode region and the second channel region are in a p-doped state, and
the cathode region and the first channel region are in an n-doped state.
12 . The stateful logic-in-memory according to claim 1 , wherein, when an electrostatically doped electrode is deposited on the first channel region, each of the plural memory cells electrically dopes the first channel region by a work function of the electrostatic doping electrode by grounding the electrostatic doping electrode, or electrically dopes the first channel region through an electric field applied by applying voltage to the electrostatic doping electrode.