Power converter
Circuits and methods for protecting a multi-level power converter using no more than two high-voltage FET switches while allowing all or most other power switches to be low-voltage FET switches. Some embodiments provide protective high-voltage top and bottom FETs designed to saturate before the remaining low-power FET switches saturate. Other embodiments may use only low-power FETs for the power switches but provide protective circuits configured to be in an always-ON (conducting) state when in normal power conversion operation, and to quickly switch to an OFF (non-conducting) state in the event of transients or a fault condition. Optionally, one or more of the protective circuits may be used in a controlled manner to limit or block current flow during certain types of fault conditions and/or to limit in-rush current during startup of a power converter.
1. A power converter, including:
(a) a set of one or more power switches coupled in series, the set including a first power switch configured to be coupled to an input terminal and a last power switch configured to be coupled to a reference voltage;
(b) a first protective switch having a control input for setting the first protective switch to an open state or to a closed state, the first protective switch coupled between the first power switch and an adjacent power switch in the set of one or more power switches; and
(c) a second protective switch configured to be coupled to a reference voltage and having a control input for setting the second protective switch to an open state or to a closed state, the second protective switch coupled between the last power switch and an adjacent power switch in the set of one or more power switches;
wherein the first protective switch and the second protective switch are set to the closed state during normal operation of the power converter, and wherein at least one of the first protective switch and the second protective switch is set to the open state in response to one or more events.
2. The power converter of claim 1 , wherein the one or more events are transient events or fault events.
3. The power converter of claim 1 , wherein the power converter is a multi-level power converter.
4. The power converter of claim 1 , wherein the power switches in the set have a saturation characteristic that is greater than the saturation characteristic of the first and second protective switches.
5. The power converter of claim 4 , wherein at least one power switch in the set of one or more power switches has a breakdown characteristic that is less than respective breakdown characteristics of the first and second protective switches.
6. The power converter of claim 1 , further including a first switch controller coupled directly or indirectly to the control input of the first protective switch and a second switch controller coupled directly or indirectly to the control input of the second protective switch, wherein at least one of the first switch controller and the second switch controller sets the associated coupled protective switch to the open state in response to the one or more events.
7. The power converter of claim 6 , wherein the one or more events are transient events or fault events.
8. The power converter of claim 1 , wherein the first protective switch is a P-type FET and the second protective switch is an N-type FET.
9. The power converter of claim 1 , further including a first voltage source coupled between the control input of the first protective switch and the input terminal, and a second voltage source coupled between the control input of the second protective switch and a reference voltage.
10. The power converter of claim 9 , wherein the first voltage source is set to a voltage greater than or equal to a breakdown voltage of the first power switch, and the second voltage source is set to a voltage greater than or equal to a breakdown voltage of the last power switch.
11. A multi-level power converter based on field-effect transistors (FETs), including:
(a) a set of one or more FET power switches coupled in series, the set including a first FET power switch configured to be coupled to an input voltage source and a last FET power switch configured to be coupled to a reference voltage;
(b) a P-type FET switch having a control input for setting the P-type FET switch to an open state or to a closed state, the P-type FET switch coupled between the first FET power switch and a next FET power switch in the set of one or more FET power switches, the P-type FET switch having a first breakdown characteristic and a first saturation characteristic;
(c) an N-type FET switch having a control input for setting the N-type FET switch to an open state or to a closed state, the N-type FET switch coupled between the last FET power switch and a preceding FET power switch in the set of one or more FET power switches, the N-type FET switch having a second breakdown characteristic and a second saturation characteristic; and
wherein the P-type FET switch and the N-type FET switch are set to the closed state during normal operation of the multi-level power converter;
wherein at least one of the P-type FET switch and the N-type FET switch is set to the open state in response to one or more events; and
wherein the FET power switches in the set have a breakdown characteristic that is less than the first breakdown characteristic and the second breakdown characteristic, and have a saturation characteristic that is greater than the first saturation characteristic and the second saturation characteristic.
12. The multi-level power converter of claim 11 , further including a circuit coupled between the control input of the N-type FET switch and a reference voltage and configured to provide a voltage difference.
13. The multi-level power converter of claim 11 , further including a circuit coupled between the control input of the P-type FET switch and the input voltage source and configured to provide a voltage difference.
14. The multi-level power converter of claim 11 , further including a first voltage source coupled between the control input of the P-type FET switch and an input terminal, and a second voltage source coupled between the control input of the N-type FET switch and a reference voltage, wherein the first voltage source is set to a voltage greater than or equal to a breakdown voltage of the P-type FET power switch, and the second voltage source is set to a voltage greater than or equal to a breakdown voltage of the N-type FET power switch.
15. The multi-level power converter of claim 11 , wherein the one or more events are transient events or fault events.
16. A power converter based on, including:
(a) a set of one or more power switches coupled in series, the set including a first power switch configured to be coupled to a voltage; and
(b) a protective switch having a control input for setting the protective switch to an open state or to a closed state, the protective switch coupled between the first power switch and an adjacent power switch in the set of one or more power switches;
wherein the protective switch is set to the closed state during normal operation of the power converter based on a breakdown characteristic and/or a saturation characteristic of the set of one or more power switches, and is set to the open state in response to one or more events.
17. The power converter of claim 16 , wherein the one or more events are transient events or fault events.
18. The power converter of claim 16 , wherein the power switches in the set of one or more power switches have a saturation characteristic that is greater than the saturation characteristic of the protective switch.
19. The power converter of claim 18 , wherein at least one power switch in the set of one or more power switches has a breakdown characteristic that is less than a break-down characteristic of the protective switch.
20. The power converter of claim 16 , further including a switch controller coupled directly or indirectly to the control input of the protective switch, wherein the switch controller sets the protective switch to the open state in response to the one or more events.