Granted Patent B2

US 12,388,007 · App. 18/582,162 · Granted Aug 12, 2025

Inventor: Prity Kirit Patel (Cary, NC)

Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.

H01L23/5223H10D1/68H10D84/811

Abstract

Claims (41)

1. A capacitor network formed on a substrate, comprising:

a bond pad over a top side of the substrate; and

a plurality of metal-insulator-metal (MIM) capacitors positioned over the top side of the substrate and along a plurality of different sides of the bond pad, wherein:

a first metal layer of each of the plurality of MIM capacitors is electrically coupled to the bond pad by a first metal trace that extends across and over the top side of the substrate between the first metal layer of the MIM capacitor and the bond pad; and

a second metal layer of each of the plurality of MIM capacitors is electrically coupled to a ground plane on a bottom side of the substrate by a second metal trace that extends across and over the top side of the substrate between the second metal layer of the MIM capacitor and a through-substate via.

2. The capacitor network according to claim 1 , further comprising a plurality of through-substate vias positioned along a number of different sides of a MIM capacitor among the plurality of MIM capacitors.

3. The capacitor network according to claim 1 , wherein each MIM capacitor among the plurality of MIM capacitors is electrically coupled to the ground plane by a plurality of through-substrate vias.

4. The capacitor network according to claim 1 , wherein the plurality of MIM capacitors are positioned along four different sides of the bond pad.

5. The capacitor network according to claim 1 , wherein:

the capacitor network comprises a plurality of bond pads; and

the plurality of MIM capacitors are electrically coupled to the plurality of bond pads.

6. An integrated device, comprising:

a power transistor formed on a first substrate;

a capacitor network formed on a second substrate, the capacitor network comprising:

a bond pad over a top side of the second substrate; and

a plurality of metal-insulator-metal (MIM) capacitors positioned over the top side of the second substrate and along a plurality of different sides of the bond pad, wherein:

a first metal layer of each of the plurality of MIM capacitors is electrically coupled to the bond pad by a first metal trace that extends across and over the top side of the second substrate between the first metal layer of the MIM capacitor and the bond pad; and

a second metal layer of each of the plurality of MIM capacitors is electrically coupled to a ground plane on a bottom side of the second substrate by a second metal trace that extends across and over the top side of the second substrate between the second metal layer of the MIM capacitor and a through-substate via; and

at least one bond wire electrically coupled between the power transistor and the bond pad of the capacitor network.

7. The integrated device according to claim 6 , further comprising a plurality of through-substate vias positioned along a number of different sides of a MIM capacitor among the plurality of MIM capacitors.

8. The integrated device according to claim 6 , wherein each MIM capacitor among the plurality of MIM capacitors is electrically coupled to the ground plane by a plurality of through-substrate vias.

9. The integrated device according to claim 6 , wherein the plurality of MIM capacitors are positioned along four different sides of the bond pad.

10. The integrated device according to claim 6 , wherein:

the capacitor network comprises a plurality of bond pads; and

the plurality of MIM capacitors are electrically coupled to the plurality of bond pads.

11. The integrated device according to claim 6 , wherein the first substrate and the second substrate are arranged together in a single device package of the integrated device.

12. The integrated device according to claim 6 , further comprising:

a second capacitor network formed on a third substrate; and

at least one bond wire electrically coupled between the power transistor and the second capacitor network, wherein the first substrate, the second substrate, and the third substrate are arranged together in a single device package of the integrated device.

13. A capacitor network, comprising

a bond pad over a substrate; and

a plurality of metal-insulator-metal (MIM) capacitors positioned over the substrate and along a plurality of different sides of the bond pad, wherein:

a first metal layer of each of the plurality of MIM capacitors is electrically coupled to the bond pad by a first metal trace that extends across and over the substrate between the first metal layer of the MIM capacitor and the bond pad; and

a second metal layer of each of the plurality of MIM capacitors is electrically coupled to a ground plane by a second metal trace that extends across and over the substrate between the second metal layer of the MIM capacitor and a through-substate via.

14. The capacitor network according to claim 13 , wherein each MIM capacitor among the plurality of MIM capacitors is electrically coupled to the ground plane by a plurality of through-substrate vias.

15. The capacitor network according to claim 1 , wherein each MIM capacitor among the plurality of MIM capacitors has a same capacitance.

16. The capacitor network according to claim 1 , wherein each MIM capacitor among the plurality of MIM capacitors has a different capacitance.

17. The integrated device according to claim 6 , wherein each MIM capacitor among the plurality of MIM capacitors has a same capacitance.

18. The integrated device according to claim 6 , wherein each MIM capacitor among the plurality of MIM capacitors has a different capacitance.

19. The capacitor network according to claim 13 , wherein each MIM capacitor among the plurality of MIM capacitors has a same capacitance.

20. The capacitor network according to claim 13 , wherein each MIM capacitor among the plurality of MIM capacitors has a different capacitance.

Assignments (1)

Continuity (2)

References Cited (36)