IP Library › Granted Patent US 12,547,327
Granted Patent B2
US 12,547,327 · App. 18/586,350 · Granted Feb 10, 2026

Program speed compensation for non-volatile memory cells

Inventors: Yi Song (San Jose, CA); Xian Liu (Sunnyvale, CA); Jinho Kim (Saratoga, CA)
Assignee: Silicon Storage Technology, Inc.
G06F3/0625G06F3/0659G06F3/0673
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Quick Facts
Patent No.
US 12,547,327
App. No.
18/586,350
Granted
Feb 10, 2026
Kind
B2
Abstract

A method of programming memory cells that includes reading the memory cells to determine respective read currents for the memory cells. Respective ones of the memory cells are assigned to one of a plurality of groups of the memory cells, wherein respective ones of the plurality of groups of the memory cells are associated with a different range of read currents, such that the determined read current for a respective one of the memory cells is within the range of read currents for the group of the memory cells to which the memory cell is assigned. The memory cells are programmed using program currents that vary for respective ones of the memory cells depending upon the group of the memory cells to which the memory cell is assigned.

Claims (110)

1 . A method of programming memory cells, comprising:

reading the memory cells to determine respective read currents for the memory cells;

assigning respective ones of the memory cells to one of a plurality of groups of the memory cells, wherein respective ones of the plurality of groups of the memory cells are associated with a different range of read currents, such that the determined read current for a respective one of the memory cells is within the range of read currents for the group of the memory cells to which the memory cell is assigned; and

programming the memory cells using program currents that vary for respective ones of the memory cells depending upon the group of the memory cells to which the memory cell is assigned.

2 . The method of claim 1 , comprising:

erasing the memory cells before the reading of the memory cells.

3 . The method of claim 1 , comprising:

pre-programming the memory cells before the reading of the memory cells.

4 . The method of claim 1 , wherein:

the plurality of groups of the memory cells comprises at least a first group, a second group and a third group;

the first group is associated with a range of read currents less than a first reference read current;

the second group is associated with a range of read currents greater than the first reference read current and less than a second reference read current;

the third group is associated with a range of read currents greater than the second reference read current;

the programming of the memory cells assigned to the first group comprising using a first program current;

the programming of the memory cells assigned to the second group comprising using a second program current;

the programming of the memory cells assigned to the third group comprising using a third program current;

the first program current is less than the second program current; and

the second program current is less than the third program current.

5 . The method of claim 1 , wherein after the programming, the method comprising:

reading the memory cells to determine respective second read currents for the memory cells;

programming those of the memory cells having a second read current greater than a reference read current using a first program current; and

programming those of the memory cells having a second read current less than the reference read current using a second program current that is less than the first program current.

6 . A method of programming memory cells, comprising:

reading the memory cells to determine respective first read currents for the memory cells;

pre-programming the memory cells after the reading of the memory cells;

reading the memory cells after the pre-programming of the memory cells to determine respective second read currents for the memory cells;

assigning respective ones of the memory cells to one of a plurality of groups of the memory cells, wherein respective ones of the plurality of groups of the memory cells are associated with a different range of read current differentials, such that a read current differential between the first and second read currents and for a respective one of the memory cells is within the range of read current differentials for the group of the memory cells to which the memory cell is assigned; and

programming the memory cells using program currents that vary for respective ones of the memory cells depending upon the group of the memory cells to which the memory cell is assigned.

7 . The method of claim 6 , comprising:

erasing the memory cells before the reading of the memory cells.

8 . The method of claim 6 , comprising:

pre-programming the memory cells before the reading of the memory cells.

9 . The method of claim 6 , wherein:

the plurality of groups of the memory cells comprises at least a first group, a second group and a third group;

the first group is associated with a range of read current differentials greater than a first reference differential;

the second group is associated with a range of read current differentials greater than the first reference differential and less than a second reference differential;

the third group is associated with a range of read current differentials greater than the second reference differential;

the programming of the memory cells assigned to the first group comprising using a first program current;

the programming of the memory cells assigned to the second group comprising using a second program current;

the programming of the memory cells assigned to the third group comprising using a third program current;

the first program current is less than the second program current; and

the second program current is less than the third program current.

10 . The method of claim 6 , wherein after the programming, the method comprising:

reading the memory cells to determine respective second read currents for the memory cells;

programming those of the memory cells having a second read current greater than a reference read current using a first program current; and

programming those of the memory cells having a second read current less than the reference read current using a second program current that is less than the first program current.

11 . A method of programming memory cells, comprising:

programming memory cells;

reading the memory cells to determine respective read currents for the memory cells relative to a target read current and a reference read current, wherein the reference read current is greater than the target read current;

programming those of the memory cells having a read current greater than a reference read current using a first program current;

programming those of the memory cells having a read current less than the reference read current and greater than the target read current using a second program current that is less than the first program current; and

ceasing programming those of the memory cells having a read current less than the target read current.

12 . A memory device, comprising:

memory cells; and

a control circuitry to:

read the memory cells to determine respective read currents for the memory cells;

assign respective ones of the memory cells to one of a plurality of groups of the memory cells, wherein respective ones of the plurality of groups of the memory cells are associated with a different range of read currents, such that the determined read current for a respective one of the memory cells is within the range of read currents for the group of the memory cells to which the memory cell is assigned; and

program the memory cells using program currents that vary for respective ones of the memory cells depending upon the group of the memory cells to which the memory cell is assigned.

13 . The memory device of claim 12 , wherein the control circuitry to:

erase the memory cells before the read of the memory cells.

14 . The memory device of claim 12 , wherein the control circuitry to:

pre-program the memory cells before the read of the memory cells.

15 . The memory device of claim 12 , wherein:

the plurality of groups of the memory cells comprises at least a first group, a second group and a third group;

the first group is associated with a range of read currents less than a first reference read current;

the second group is associated with a range of read currents greater than the first reference read current and less than a second reference read current;

the third group is associated with a range of read currents greater than the second reference read current;

the program of the memory cells assigned to the first group comprises using a first program current;

the program of the memory cells assigned to the second group comprises using a second program current;

the program of the memory cells assigned to the third group comprises using a third program current;

the first program current is less than the second program current; and

the second program current is less than the third program current.

16 . The memory device of claim 12 , wherein after the program of the memory cells, the control circuitry to:

read the memory cells to determine respective second read currents for the memory cells;

program those of the memory cells having a second read current greater than a reference read current using a first program current; and

program those of the memory cells having a second read current less than the reference read current using a second program current that is less than the first program current.

17 . A memory device, comprising:

memory cells; and

a control circuitry to:

read the memory cells to determine respective first read currents for the memory cells;

pre-program the memory cells after the read of the memory cells;

read the memory cells after the pre-program of the memory cells to determine respective second read currents for the memory cells;

assign respective ones of the memory cells to one of a plurality of groups of the memory cells, wherein respective ones of the plurality of groups of the memory cells are associated with a different range of read current differentials, such that a read current differential between the first and second read currents and for a respective one of the memory cells is within the range of read current differentials for the group of the memory cells to which the memory cell is assigned; and

program the memory cells using program currents that vary for respective ones of the memory cells depending upon the group of the memory cells to which the memory cell is assigned.

18 . The memory device of claim 17 , wherein the control circuitry to:

erase the memory cells before the read of the memory cells.

19 . The memory device of claim 17 , wherein the control circuitry to:

pre-program the memory cells before the read of the memory cells.

20 . The memory device of claim 17 , wherein:

the plurality of groups of the memory cells comprises at least a first group, a second group and a third group;

the first group is associated with a range of read current differentials greater than a first reference differential;

the second group is associated with a range of read current differentials greater than the first reference differential and less than a second reference differential;

the third group is associated with a range of read current differentials greater than the second reference differential;

the program of the memory cells assigned to the first group comprises using a first program current;

the program of the memory cells assigned to the second group comprises using a second program current;

the program of the memory cells assigned to the third group comprises using a third program current;

the first program current is less than the second program current; and

the second program current is less than the third program current.

21 . The memory device of claim 17 , wherein after the program of the memory cells, the control circuitry to:

read the memory cells to determine respective second read currents for the memory cells;

program those of the memory cells having a second read current greater than a reference read current using a first program current; and

program those of the memory cells having a second read current less than the reference read current using a second program current that is less than the first program current.

22 . A memory device, comprising:

memory cells; and

a control circuitry to:

program the memory cells;

read the memory cells to determine respective read currents for the memory cells relative to a target read current and a reference read current, wherein the reference read current is greater than the target read current;

program those of the memory cells having a read current greater than a reference read current using a first program current;

program those of the memory cells having a read current less than the reference read current and greater than the target read current using a second program current that is less than the first program current; and

cease programming those of the memory cells having a read current less than the target read current.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2024
From: SONG, YI; LIU, XIAN; KIM, JINHO
To: SILICON STORAGE TECHNOLOGY, INC.
Reel/Frame 066550/0392 →
Continuity (2)
Provisional Application 63606008 · Dec 4, 2023
Related Publication 20250181255A1 · Jun 5, 2025
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