IP Library Granted Patent US 12,347,755
Granted Patent B2
US 12,347,755 · App. 18/592,704 · Granted Jul 1, 2025

Low stress asymmetric dual side module

Inventors: Chee Hiong Chew (Seremban, MY); Atapol Prajuckamol (Thanyaburi, TH); Stephen St. Germain (Gilbert, AZ); Yusheng Lin (Phoenix, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L23/49575H01L23/367H01L23/4093H01L23/49568H01L23/49582H01L24/80H01L25/0657
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Quick Facts
Patent No.
US 12,347,755
App. No.
18/592,704
Granted
Jul 1, 2025
Kind
B2
Abstract

Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

Claims (41)

1. A method of forming semiconductor packages, the method comprising:

providing a first panel of a plurality of first substrates and a second panel of a plurality of second substrates;

printing a first sintering material on the first panel of the plurality of first substrates and the second panel of the plurality of second substrates in predetermined locations;

coupling two or more die to each of the first panel of the plurality of first substrates and the second panel of the plurality of second substrates at the predetermined locations;

dispensing a second sintering material onto each of the two or more die;

coupling a clip to each of the two or more die;

electrically coupling the two or more die to the plurality of first substrates and the plurality of second substrates;

singulating the first panel and the second panel into the plurality of first substrates and the plurality of second substrates, respectively;

dispensing solder onto a plurality of predetermined locations on a first substrate of the first plurality of substrates and a second substrate of the second plurality of substrates;

coupling the first substrate of the plurality of first substrates to a first side of a lead frame; and

coupling the second substrate of the plurality of second substrates to a second side of the lead frame.

2. The method of claim 1 , further comprising trimming the lead frame to expose a plurality of leads.

3. The method of claim 1 , further comprising encapsulating the lead frame on the first side and the second side, wherein a second side of each of the first substrate and the second substrate is exposed.

4. The method of claim 1 , further comprising directly coupling the clip to the first substrate and the second substrate through the first sintering material.

5. The method of claim 1 , further comprising coupling a heat sink with one of the first substrate, the second substrate, or any combination thereof.

6. The method of claim 1 , further comprising coupling one or more leads with one of a C-shaped or S-shaped cross sectional shape between the first substrate and the second substrate.

7. The method of claim 1 , wherein the first substrate and the second substrate are asymmetrically coupled through the lead frame.

8. A method of forming a semiconductor package, the method comprising:

coupling a first die to a first substrate through a first sintering material;

coupling a second die to a second substrate through a second sintering material;

coupling a first clip to the first die through a third sintering material;

coupling a second clip to the second die through a fourth sintering material;

coupling the first substrate to a lead frame;

coupling the second substrate to the lead frame, wherein the lead frame is directly coupled to and between the first substrate and the second substrate upon coupling the second substrate to the lead frame; and

partially encapsulating the lead frame in a molding compound.

9. The method of claim 8 , wherein only a portion of the first substrate is coupled directly under the second substrate and only a portion of the second substrate is coupled directly over the first substrate.

10. The method of claim 8 , further comprising coupling a heat sink with one of the first substrate, the second substrate, or any combination thereof.

11. The method of claim 8 , further comprising coupling one or more leads with one of a C-shaped or S-shaped cross sectional shape between the first substrate and the second substrate.

12. The method of claim 8 , further comprising coupling a third die to the first substrate through the first sintering material, coupling a fourth die to the second substrate through the second sintering material, coupling a third clip to the third die through the third sintering material, and coupling a fourth clip to the fourth die through the fourth sintering material.

13. The method of claim 11 , wherein the one or more leads is directly coupled to a terminal of the first substrate and a terminal of the second substrate and wherein the terminal of the first substrate is aligned with the terminal of the second substrate.

14. The method of claim 11 , wherein the one or more leads is directly coupled to a terminal of the first substrate and a terminal of the second substrate and wherein the terminal of the first substrate is misaligned with the terminal of the second substrate.

15. A method of forming a semiconductor package, the method comprising:

coupling a first die to a first substrate through a first sintering material;

coupling a second die to a second substrate through a second sintering material; and

asymmetrically coupling the first substrate to the second substrate through a lead frame that is directly coupled to the first substrate and the second substrate; and

at least partially encapsulating the lead frame in a molding compound.

16. The method of claim 15 , further comprising coupling a plurality of clips to the first substrate and the second substrate.

17. The method of claim 15 , wherein a perimeter of a first side of the first substrate extends outside of a perimeter of a first side of the second substrate and the perimeter of the first side of the second substrate extends outside of the perimeter of the first side of the first substrate, wherein the first side of the first substrate faces the first side of the second substrate.

18. The method of claim 15 , further comprising coupling one or more leads with a cross sectional shape that provides separation between the first substrate and the second substrate.

19. The method of claim 15 , further comprising coupling a first clip directly to the first die through a third sintering material and coupling a second clip directly to the second die through a fourth sintering material.

20. The method of claim 15 , further comprising coupling a first clip directly to the first substrate through the first sintering material and coupling a second clip directly to the second substrate through the second sintering material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2024
From: ST. GERMAIN, STEPHEN; LIN, YUSHENG; CHEW, CHEE HIONG; PRAJUCKAMOL, ATAPOL
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 066613/0390 →
Continuity (5)
Continuation 17929898 · Sep 6, 2022
Division 16733322 · Jan 3, 2020
Continuation In Part 16678039 · Nov 8, 2019
Provisional Application 62882119 · Aug 2, 2019
Related Publication 20240203845A1 · Jun 20, 2024
References Cited (57)
US 4763188A · Johnson · 1988 [cited by examiner]
US 5332921A · Dousen et al. · 1994 [cited by applicant]
US 5452182A · Eichelberger et al. · 1995 [cited by applicant]
US 5615475A · Burns · 1997 [cited by examiner]
US 6175149B1 · Akram · 2001 [cited by examiner]
US 6239496B1 · Asada · 2001 [cited by examiner]
US 6421244B1 · Shinohara et al. · 2002 [cited by applicant]
US 6545345B1 · Glenn · 2003 [cited by examiner]
US 6618267B1 · Dalal et al. · 2003 [cited by applicant]
US 6677665B2 · Huang · 2004 [cited by applicant]
US 7438558B1 · Sinha · 2008 [cited by applicant]
US 7468553B2 · Szewerenko · 2008 [cited by examiner]
US 7517733B2 · Camacho · 2009 [cited by examiner]
US 7569921B2 · Okane et al. · 2009 [cited by applicant]
US 7612434B2 · Imaizumi · 2009 [cited by examiner]
US 7692279B2 · Karnezos · 2010 [cited by examiner]
US 10242969B2 · Hohlfeld et al. · 2019 [cited by applicant]
US 10418313B2 · Fuergut et al. · 2019 [cited by applicant]
US 11462515B2 · Chew · 2022 [cited by examiner]
US 11469163B2 · Chew · 2022 [cited by examiner]
US 11830856B2 · Chew · 2023 [cited by examiner]
US 11894347B2 · Chew · 2024 [cited by examiner]
US 11908840B2 · Chew · 2024 [cited by examiner]
US 11948870B2 · Chew · 2024 [cited by examiner]
US 11955412B2 · Chew · 2024 [cited by examiner]
US 20020005575A1 · Park · 2002 [cited by examiner]
US 20040070083A1 · Su · 2004 [cited by applicant]
US 20040113253A1 · Karnezos · 2004 [cited by applicant]
US 20050110127A1 · Kanemoto et al. · 2005 [cited by applicant]
US 20070018313A1 · Gomyo et al. · 2007 [cited by applicant]
US 20070099437A1 · Hable · 2007 [cited by applicant]
US 20080230928A1 · Otremba · 2008 [cited by examiner]
US 20080315381A1 · Yoshida · 2008 [cited by applicant]
US 20090108467A1 · Otremba · 2009 [cited by examiner]
US 20090116197A1 · Funakoshi et al. · 2009 [cited by applicant]
US 20110037166A1 · Ikeda et al. · 2011 [cited by applicant]
US 20110057713A1 · Kawanami · 2011 [cited by examiner]
US 20120307541A1 · Shimoike · 2012 [cited by examiner]
US 20130154110A1 · Gowda · 2013 [cited by applicant]
US 20140087520A1 · Funatsu et al. · 2014 [cited by applicant]
US 20140159216A1 · Ishino et al. · 2014 [cited by applicant]
US 20150092375A1 · Otremba et al. · 2015 [cited by applicant]
US 20150179611A1 · Lu et al. · 2015 [cited by applicant]
US 20160064308A1 · Yamada · 2016 [cited by applicant]
US 20170062316A1 · Mukhopadhyay · 2017 [cited by examiner]
US 20170117209A1 · Benedikt · 2017 [cited by examiner]
US 20170287875A1 · Gao · 2017 [cited by examiner]
US 20170317015A1 · Lee et al. · 2017 [cited by applicant]
US 20180082921A1 · Grassmann · 2018 [cited by examiner]
US 20180122720A1 · Hable · 2018 [cited by examiner]
US 20180166415A1 · Khaselev · 2018 [cited by examiner]
US 20180240731A1 · Choi · 2018 [cited by examiner]
US 20190122964A1 · Mangrum · 2019 [cited by applicant]
US 20190393137A1 · Yandoc et al. · 2019 [cited by applicant]
US 20200135626A1 · Yong et al. · 2020 [cited by applicant]
US 20200194364A1 · Duran et al. · 2020 [cited by applicant]
WO 2019037867A1 · 2019 [cited by applicant]