Gate driver
A gate driver includes: a gate driving circuit configured to generate a gate driving signal for a power device according to a gate control signal; and a driving capacity switch circuit configured to raise the gate driving capacity of the gate driving circuit when a time-variation signal obtained by passing the gate driving signal in the on-transition period of the power device through a high-pass filter becomes lower than a threshold value.
1 . A gate driver, comprising:
a gate driving circuit configured to generate a gate driving signal for a power device according to a gate control signal; and
a driving capacity switch circuit configured to raise a gate driving capacity of the gate driving circuit when a time-variation signal obtained by passing the gate driving signal in an on-transition period of the power device through a high-pass filter becomes lower than a threshold value, wherein
the gate driving circuit includes:
a first gate driver configured to charge a gate capacitance of the power device by constant-current driving;
a second gate driver configured to charge the gate capacitance of the power device by voltage driving; and
a logic gate configured to enable and disable the second gate driver according to an instruction from the driving capacity switch circuit,
the first gate driver includes a constant current source,
the constant current source is configured to be connected between a power terminal and a gate of the power device,
the second gate driver includes a switch and a resistor, and
the switch and the resistor are connected in series between the power terminal and the gate of the power device.
2 . The gate driver according to claim 1 , wherein
the driving capacity switch circuit includes:
the high-pass filter configured to generate the time-variation signal by extracting from the gate driving signal a component of a frequency higher than a cutoff frequency;
a comparator configured to compare the time-variation signal with the threshold value to generate a comparison signal; and
a latch configured to receive the gate control signal and the comparison signal to generate a driving capacity switch signal for the gate driving circuit.
3 . The gate driver according to claim 2 , wherein
the latch is
in a reset state when the gate control signal is at a logic level corresponding to an off state and
is in a reset-released state when the gate control signal is at a logic level corresponding to an on state.
4 . The gate driver according to claim 2 , wherein
the driving capacity switch circuit further includes a delay circuit configured to delay and then output the gate control signal to the latch.
5 . The gate driver according to claim 1 , wherein
the high-pass filter is a first-order CR high-pass filter including a capacitor and a resistor.
6 . The gate driver according to claim 1 , wherein
the threshold value is a variable value.
7 . The gate driver according to claim 1 , wherein
the gate driving circuit includes:
a first gate driver; and
a second gate driver configured to have a different driving capacity from the first gate driver, and
the first and second gate drivers are enabled and disabled individually and exclusively according to an instruction from the driving capacity switch circuit.
8 . The gate driver according to claim 1 , wherein
the gate driving circuit and the driving capacity switch circuit are both integrated in a semiconductor device.