Quantum computing
According to the invention, there is provided a timing system for an ion trap quantum computer comprising a clock outputting a timing signal of period t, a plurality of delay lines coupled to the clock and each configured to input a different delay of less than t and a delay selection mechanism configured to select the delay wherein the delay by each of the delay lines is a different fraction of the period t.
1 . A quantum computer comprising:
a quantum processor communicatively coupled to:
(a) a clock, wherein the clock is configured to transmit a clock signal;
(b) a plurality of delay signal lines, wherein each delay signal line in the plurality of delay signal lines is configured to receive the clock signal and add a different delay to the clock signal to generate an amended clock signal, thereby forming a plurality of amended clock signals; and
(c) a delay selection mechanism, wherein the delay selection mechanism is coupled to a digital-to-analog converter (DAC), and wherein the delay selection mechanism is configured to select an amended clock signal from the plurality of amended clock signals to be applied to the DAC and to control the timing of a gate operation.
2 . The system of claim 1 , wherein the clock signal is a pulse signal.
3 . The system of claim 1 , further comprising a buffer, wherein the buffer is configured to transmit the clock signal to each delay signal line of the plurality of delay signal lines.
4 . The system of claim 1 , wherein each delay associated with the plurality of delay signal lines is less than 10 μs.
5 . The system of claim 1 , further comprising an ion trap, wherein the ion trap comprises the DAC and an electrode, wherein the electrode corresponds to the DAC.
6 . The system of claim 5 , wherein the ion trap is configured to have a motional trap frequency of period t.
7 . The system of claim 6 , wherein the amended clock signal is less than ‘t’.
8 . The system of claim 7 , wherein the delay of each delay signal line in the plurality of delay signal lines is t*x/n, wherein ‘n’ is a number of delay signal lines and ‘x’ is a positive integer between 0 and n−1.
9 . The system of claim 5 , wherein the ion trap further comprises a plurality of DACs, wherein each DAC of the plurality of DACs has a corresponding electrode, plurality of delay lines, and delay selection mechanism, and wherein the clock is configured to output substantially the same timing signal to each delay line in each plurality of delay lines.
10 . The system of claim 9 , wherein the ion trap comprises direct current (DC) DACs and radio frequency (RF) DACs.
11 . The system of claim 6 , wherein the motional trap frequency is from about 100 kHz to about 1000 kHz.
12 . The system of claim 10 , wherein the RF electrodes are configured to emit a signal having a frequency of about 10 MHz to about 40 MHz.
13 . The system of claim 9 , wherein the electrodes are arranged in an x-junction device.
14 . The system of claim 13 , wherein x-junction device comprises a plurality of areas, and wherein the electrodes are configured to trap an ion in an area of the plurality of areas of the x-junction device.
15 . The system of claim 14 , wherein the area of the x-junction device is a crystal operations area, junction shuttling area, logic region/gate zone area, or linear shuttling area.
16 . The system of claim 13 , wherein the x-junction device comprises four sections.
17 . The system of claim 16 , wherein the system is configured to selectively apply a signal to a section of the four sections based at least in part on an occupancy of an ion in the section.
18 . The system of claim 5 , wherein the ion trap is configured to trap an ion selected from the group consisting of 171 Yb + , 40 Ca + , 43 Ca + , 9 Be + , Sr + , and Hg + .
19 . A method comprising:
(a) generating a plurality of clock signals;
(b) adding a different delay to each clock signal in the plurality of clock signals to generate a plurality of amended clock signals;
(c) selecting, by a delay selection mechanism, an amended clock signal from the plurality of amended clock signals; and
(d) applying the amended clock signal to a digital-to-analog converter (DAC), wherein the DAC is configured to control a gate operation in a quantum processor.
20 . The method of claim 19 , wherein adding a different delay to each clock signal in (b) is performed, at least in part, using a plurality of delay signal lines.
21 . The method of claim 20 , wherein adding a different delay to each clock signal in (b) further comprises a buffer configured to transmit each clock signal of the plurality of clock signals to a delay signal line of the plurality of delay signal lines.
22 . The method of claim 19 , wherein the quantum processor comprises an ion trap.
23 . The method of claim 22 , wherein the ion trap is configured to have a motional trap frequency of period t.
24 . The method of claim 23 , wherein the amended clock signal is less than ‘t’.
25 . The method of claim 24 , wherein adding a different delay to each clock signal in (b) comprises a delay of t * x/n, wherein ‘n’ is a number of delay signal lines of the plurality of delay signal lines and ‘x’ is a positive integer between 0 and n-1.
26 . The method of claim 22 , wherein the ion trap further comprises a plurality of DACs, wherein each DAC of the plurality of DACs has a corresponding electrode, plurality of delay lines, and delay selection mechanism, the method further comprising outputting substantially the same timing signal to each delay line in each plurality of delay lines.
27 . The method of claim 26 , wherein the electrodes are arranged in an x-junction device.
28 . The method of claim 27 , wherein x-junction device comprises a plurality of areas, the method further comprising trapping, using the electrodes, an ion in an area of the plurality of areas of the x-junction device.
29 . The method of claim 28 , wherein the area of the x-junction device is a crystal operations area, junction shuttling area, logic region/gate zone area, or linear shuttling area.