IP Library Granted Patent US 12,493,567
Granted Patent B2
US 12,493,567 · App. 18/599,738 · Granted Dec 9, 2025

Storage apparatus and control method for storage apparatus

Inventors: Norio Chujo (Tokyo, JP); Masanori Takada (Tokyo, JP)
Assignee: Hitachi, Ltd.
G06F13/1663G06F12/0868G06F13/1668
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Quick Facts
Patent No.
US 12,493,567
App. No.
18/599,738
Granted
Dec 9, 2025
Kind
B2
Abstract

A storage apparatus includes a first controller having a first memory, a second controller having a second memory, and a memory module having a third memory. The first memory stores drive control information including a correspondence between a logical address and a physical address, first cache data in a data input-output (I/O) process, and first cache control information including a correspondence between a logical address and a cache address of the first cache data. The second memory stores drive control information, second cache data in the data I/O process, and second cache control information including a correspondence between a logical address and a cache address of the second cache data. The third memory stores first cache data provided with redundancy and second cache data provided with redundancy.

Claims (64)

1 . A storage apparatus that is communicably connected to another apparatus and executes a data input-output process in a storage device in response to a data input-output request received from the another apparatus, the storage apparatus comprising:

a first controller including a first memory;

a second controller including a second memory and being communicably connected to the first controller; and

a memory module that is communicably connected to the first controller and the second controller and includes a third memory, wherein

the first memory stores

drive control information that is information for managing a correspondence between a logical address and a physical address, the logical address being information indicating a location of data handled by the another apparatus in the data input-output process, the physical address being information indicating a location of the data in the storage device,

first cache data in the data input-output process, and

first cache control information that is information for managing a correspondence between the logical address of the first cache data and a cache address that is information indicating a location of the first cache data in the first memory,

the second memory stores

the drive control information,

second cache data in the data input-output process, and

second cache control information that is information for managing a correspondence between the logical address of the second cache data and a cache address that is information indicating a location of the second cache data in the first memory,

the third memory stores

the first cache data where a correspondence between a logical address and a cache address is managed by the first cache control information, and

the second cache data where a correspondence between a logical address and a cache address is managed by the second cache control information, and wherein

when the first controller is blocked,

the first cache data stored in the third memory is deleted,

second dirty cache data that is dirty cache data of the second cache data stored in the second memory is transferred as third dirty cache data to the third memory,

third cache control information is generated and stored in the third memory, the third cache control information being information for managing a correspondence between the logical address of the second dirty cache data and a cache address that is information indicating a location of the second dirty cache data in the third memory,

the second dirty cache data as the dirty cache data of the second cache data stored in the third memory before the blockage is transferred to the second memory,

a correspondence between the logical address of the second dirty cache data and a cache address that is information indicating a location of the second dirty cache data in the second memory is reflected in the second cache control information,

the second dirty cache data stored in the second memory is transferred to the third memory,

a correspondence between the logical address of the second dirty cache data and a cache address that is information indicating the location of the second dirty cache data in the third memory is reflected in the third cache control information, and

the drive control information stored in the second memory is transferred to the third memory.

2 . The storage apparatus according to claim 1 , wherein

when the memory module is blocked,

first dirty cache data of the first cache data in the first memory is transferred to the second memory,

the second dirty cache data of the second cache data in the second memory is transferred to the first memory,

a correspondence between the logical address of the second dirty cache data and a cache address that is information indicating a location of the second dirty cache data in the first memory is reflected in the first cache control information, and

a correspondence between the logical address of the first dirty cache data and a cache address that is information indicating a location of the first dirty cache data in the second memory is reflected in the second cache control information.

3 . The storage apparatus according to claim 1 , wherein the first controller and the second controller further include a processor, a communication interface that communicates with the another apparatus, and a drive interface that communicates with the storage device.

4 . The storage apparatus according to claim 1 , wherein the memory module further includes a memory controller that communicates with the first controller and the second controller.

5 . A storage apparatus that is communicably connected to another apparatus and executes a data input-output process in a storage device in response to a data input-output request received from the another apparatus, the storage apparatus comprising:

a first controller;

a second controller communicably connected to the first controller;

a first memory module that is communicably connected to the first controller and the second controller and includes a first memory;

a second memory module that is communicably connected to the first controller and the second controller and includes a second memory; and

a third memory module that is communicably connected to the first controller and the second controller and includes a third memory, wherein

the first memory stores

drive control information that is information for managing a correspondence between a logical address and a physical address, the logical address being information indicating a location of data handled by the another apparatus in the data input-output process, the physical address being information indicating a location of the data in the storage device,

first cache data in the data input-output process, and

first cache control information that is information for managing a correspondence between the logical address of the first cache data and a cache address that is information indicating a location of the first cache data in the first memory,

the second memory stores

the drive control information,

second cache data in the data input-output process, and

second cache control information that is information for managing a correspondence between the logical address of the second cache data and a cache address that is information indicating a location of the second cache data in the first memory,

the third memory stores

the first cache data where a correspondence between a logical address and a cache address is managed by the first cache control information, and

the second cache data where a correspondence between a logical address and a cache address is managed by the second cache control information, and wherein

when the first memory module is blocked,

the first cache data stored in the third memory is deleted,

second dirty cache data that is dirty cache data of the second cache data stored in the second memory is transferred as third dirty cache data to the third memory,

third cache control information is generated and stored in the third memory, the third cache control information being information for managing a correspondence between the logical address of the second dirty cache data and a cache address that is information indicating a location of the second dirty cache data in the third memory,

the second dirty cache data as the dirty cache data of the second cache data stored in the third memory before the blockage is transferred to the second memory,

a correspondence between the logical address of the second dirty cache data and a cache address that is information indicating a location of a second dirty cache data in the second memory is reflected in the second cache control information,

the second dirty cache data stored in the second memory is transferred to the third memory,

a correspondence between the logical address of the second dirty cache data and a cache address that is information indicating a location of the second dirty cache data in the third memory is reflected in the third cache control information, and

the drive control information stored in the second memory is transferred to the third memory.

6 . The storage apparatus according to claim 5 , wherein

when the third memory module is blocked,

first dirty cache data of the first cache data in the first memory is transferred to the second memory,

the second dirty cache data of the second cache data in the second memory is transferred to the first memory,

a correspondence between the logical address of the second dirty cache data and a cache address that is information indicating a location of the second dirty cache data in the first memory is reflected in the first cache control information, and

a correspondence between the logical address of the first dirty cache data and a cache address that is information indicating a location of the first dirty cache data in the second memory is reflected in the second cache control information.

Assignments (2)
DE-MERGER EFFECTIVE APRIL 1, 2024 Recorded Oct 1, 2024
From: HITACHI, LTD.
To: HITACHI VANTARA, LTD.
Reel/Frame 069083/0345 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2024
From: CHUJO, NORIO; TAKADA, MASANORI
To: HITACHI, LTD.
Reel/Frame 066705/0725 →
Priority Claims (1)
JP 2023-102543 · Jun 22, 2023 · national
Continuity (1)
Related Publication 20240427713A1 · Dec 26, 2024
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