Memory device
A memory cell includes first and second ends. A first interconnect is coupled to the first end. A first switch is coupled between the first interconnect and a first node that receives a first voltage. A second interconnect is coupled to the second end. A second switch includes a third end coupled to the second interconnect and a fourth end. A third interconnect is coupled to the fourth end. A third switch is coupled between the third interconnect and a second node that receives a second voltage different from the first voltage. A third voltage between the second and first voltages is applied to the first and second interconnects. The third and second switches are respectively turned off and on after the third switch is turned on and after the application of the third voltage. The first switch is turned off after the application of the third voltage.
1 . A memory device comprising:
a memory cell including a first end and a second end;
a first interconnect coupled to the first end;
a first switch coupled between the first interconnect and a first node, the first node receiving a first voltage;
a second interconnect coupled to the second end;
a second switch including a third end coupled to the second interconnect and a fourth end;
a third interconnect coupled to the fourth end;
a third switch coupled between the third interconnect and a second node, the second node receiving a second voltage different from the first voltage; and
a controller configured to:
apply a third voltage between the second voltage and the first voltage to the first interconnect and the second interconnect,
turn on the third switch,
turn off the third switch and turn on the second switch after the third switch is turned on and after the application of the third voltage, and
turn off the first switch after the application of the third voltage.
2 . The memory device according to claim 1 , wherein
the first interconnect is electrically floating while the first switch is off.
3 . The memory device according to claim 2 , wherein
the second interconnect is electrically floating while the third switch is off and the second switch is on.
4 . The memory device according to claim 1 , wherein
the second interconnect is electrically floating while the third switch is off and the second switch is on.
5 . The memory device according to claim 1 , wherein
the first switch and the second switch are maintained off during a first period,
the second switch is maintained off and the first switch is maintained on during a second period after the first period,
the first switch and the second switch are maintained off during a third period after the second period,
the third switch is maintained on until an end of the third period, and
the first switch and the third switch are maintained off and the second switch is maintained on during a fourth period after the third period.
6 . The memory device according to claim 5 , further comprising:
a fourth switch coupled between the first interconnect and a third node that receives the third voltage; and
a fifth switch coupled between the second interconnect and the third node, wherein
the fourth switch and the fifth switch are maintained on during the first period,
the fourth switch is maintained off and the fifth switch is maintained on during the second period and the third period, and
the fourth switch and the fifth switch are maintained off during the fourth period.
7 . The memory device according to claim 5 , further comprising
a sixth switch coupled between the second interconnect and a node that receives the second voltage, wherein
the sixth switch is maintained off during the first period, the second period, and the third period, and
the sixth switch is maintained on during the fourth period.
8 . The memory device according to claim 7 , wherein
the memory cell includes a variable resistance material, and
the variable resistance material includes a fifth end and a sixth end, has a first resistance between the fifth end and the sixth end once the variable resistance material receives a positive fifth voltage from the fifth end toward the sixth end, has a second resistance lower than the first resistance between the fifth end and the sixth end once the variable resistance material receives a positive sixth voltage lower than the fifth voltage from the fifth end toward the sixth end, has a third resistance between the fifth end and the sixth end once the variable resistance material receives a positive seventh voltage from the sixth end toward the fifth end, and has a fourth resistance lower than the third resistance between the fifth end and the sixth end once the variable resistance material receives a positive eighth voltage lower than the seventh voltage from the sixth end toward the fifth end.
9 . The memory device according to claim 8 , wherein
the memory cell further includes:
a first ferromagnetic layer;
a second ferromagnetic layer; and
an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer.
10 . The memory device according to claim 5 , further comprising:
a fourth interconnect coupled between the first node and the first switch; and
a seventh switch coupled between the fourth interconnect and the first node, wherein
the first switch and the second switch are maintained off and the seventh switch is maintained on during a fifth period before the first period,
the seventh switch is maintained on during the first period, and
the seventh switch is maintained off during the second period, the third period, and the fourth period.
11 . The memory device according to claim 10 , wherein
the memory cell includes a variable resistance material, and
the variable resistance material includes a fifth end and a sixth end, has a first resistance between the fifth end and the sixth end once the variable resistance material receives a positive fifth voltage from the fifth end toward the sixth end, has a second resistance lower than the first resistance between the fifth end and the sixth end once the variable resistance material receives a positive sixth voltage lower than the fifth voltage from the fifth end toward the sixth end, has a third resistance between the fifth end and the sixth end once the variable resistance material receives a positive seventh voltage from the sixth end toward the fifth end, and has a fourth resistance lower than the third resistance between the fifth end and the sixth end once the variable resistance material receives a positive eighth voltage lower than the seventh voltage from the sixth end toward the fifth end.
12 . The memory device according to claim 11 , wherein
the memory cell further includes:
a first ferromagnetic layer;
a second ferromagnetic layer; and
an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer.
13 . The memory device according to claim 1 , wherein
the memory cell includes a variable resistance material, and
the variable resistance material includes a fifth end and a sixth end, has a first resistance between the fifth end and the sixth end once the variable resistance material receives a positive fifth voltage from the fifth end toward the sixth end, has a second resistance lower than the first resistance between the fifth end and the sixth end once the variable resistance material receives a positive sixth voltage lower than the fifth voltage from the fifth end toward the sixth end, has a third resistance between the fifth end and the sixth end once the variable resistance material receives a positive seventh voltage from the sixth end toward the fifth end, and has a fourth resistance lower than the third resistance between the fifth end and the sixth end once the variable resistance material receives a positive eighth voltage lower than the seventh voltage from the sixth end toward the fifth end.
14 . The memory device according to claim 13 , wherein
the memory cell further includes:
a first ferromagnetic layer;
a second ferromagnetic layer; and
an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer.