Charge pump regulator
The present disclosure relates to a regulator including a first transistor coupling an application node of a first power supply voltage to an output node of the regulator supplying a first regulated voltage; a feedback loop supplying a control signal to the first transistor and comprising a first charge pump circuit; a control signal generator of the first charge pump circuit; and a drop-down circuit between the control signal generator and the charge pump circuit.
1 . A regulator, comprising:
a first transistor coupling an application node of a first supply voltage to an output node of the regulator to supply a first regulated voltage;
a feedback loop supplying a first control signal to the first transistor, the feedback loop including:
a first charge pump circuit; and
a first control signal generator for the first charge pump circuit; and
a step-down circuit including a buffer circuit coupled between the first control signal generator and the first charge pump circuit, the buffer circuit coupled to a power supply node configured to receive a regulated voltage that is lower than the first supply voltage, the first control signal generator coupled between the output node and the step-down circuit; and
a second charge pump circuit configured to supply a second control signal to the first transistor in case the first charge pump circuit is disabled.
2 . The regulator according to claim 1 , wherein the first control signal generator includes a clock signal generator.
3 . The regulator according to claim 2 , wherein the buffer circuit is configured to be controlled by a clock signal generated by the clock signal generator.
4 . The regulator according to claim 3 , wherein the buffer circuit includes a first inverter stage including a first PMOS transistor in series with first NMOS transistor, control nodes of the first PMOS transistor and the first NMOS transistor configured to be controlled by the clock signal, and
a node between the first PMOS transistor and the first NMOS transistor of the first inverter stage is coupled to the first charge pump circuit.
5 . The regulator according to claim 4 , wherein the buffer circuit includes a second inverter stage including a second PMOS transistor in series with a second NMOS transistor, control nodes of the second PMOS transistor and the second NMOS transistor being coupled to the node between the first PMOS transistor and the first NMOS transistor of the first inverter stage.
6 . The regulator according to claim 5 , wherein a node between the second PMOS transistor and the second NMOS transistor of the second inverter stage is coupled to the first charge pump circuit.
7 . The regulator according to claim 6 , wherein a conduction node of the first PMOS transistor or the second PMOS transistor is coupled to the power supply node of the step-down circuit.
8 . The regulator according to claim 1 , wherein the step-down circuit includes a second and third transistor each of the second and third transistor having a first conduction node coupled to the power supply node of the step-down circuit and a second conduction node coupled to the application node of the first supply voltage.
9 . The regulator according to claim 8 , wherein a control node of the second transistor is configured to receive the control signal.
10 . The regulator according to claim 8 , wherein a control node of the third transistor is coupled to an application node of a reference voltage lower than the first supply voltage.
11 . The regulator according to claim 1 , wherein the feedback loop includes a comparator circuit configured to compare the first regulated voltage to a first reference voltage, and
the first charge pump circuit is enabled or disabled in accordance with the comparison between the first regulated voltage and the first reference voltage.
12 . The regulator according to claim 1 , wherein the feedback loop includes a first comparator circuit configured to compare the first regulated voltage to a first reference voltage,
the first charge pump circuit is enabled or disabled in accordance with the comparison between the first regulated voltage and the first reference voltage, and
the regulator includes:
a second comparator circuit configured to compare the first regulated voltage with a second reference voltage lower than the first reference voltage; and
a second control signal generator, the second charge pump circuit being controlled by the second control signal generator in accordance with the comparison between the first regulated voltage and the second reference voltage.
13 . The regulator according to claim 1 , wherein the step-down circuit includes:
a second transistor coupled between the power supply node and the application node; and
an amplifier coupled to the second transistor and configured to control the second transistor based on a reference voltage.
14 . The regulator according to claim 1 , wherein the step-down circuit includes:
a second transistor coupled between the power supply node and the application node, the second transistor configured to be controlled by a reference voltage; and
a third transistor coupled to the power supply node and the application node, the third transistor being configured to be controlled by the control signal.
15 . An integrated circuit, comprising:
a regulator including:
a first transistor coupling an application node of a first supply voltage to an output node of the regulator to supply a first regulated voltage;
a feedback loop supplying a control signal to the first transistor, the feedback loop including:
a first charge pump circuit; and
a first control signal generator for the first charge pump circuit; and
a step-down circuit including a buffer circuit coupled between the first control signal generator and the first charge pump circuit, a second transistor, and third transistor,
the buffer circuit coupled to a power supply node configured to receive a regulated voltage that is lower than the first supply voltage,
the first control signal generator coupled between the output node and the step-down circuit,
each of the second and third transistors having a first conduction node coupled to the power supply node and a second conduction node coupled to the application node of the first supply voltage,
a control node of the second transistor is configured to receive the control signal; and
circuitry coupled to the regulator.
16 . The integrated circuit according to claim 15 , wherein the first control signal generator includes a clock signal generator that is coupled between the output node and the step-down circuit.
17 . The integrated circuit according to claim 15 , wherein a control node of the third transistor is coupled to an application node of a reference voltage lower than the first supply voltage.
18 . A device, comprising:
a first transistor configured to receive a supply voltage signal at an application node and supply a first regulated voltage signal using the supply voltage signal;
a clock signal generator configured to generate a clock signal;
a step-down circuit coupled to the clock signal generator, the step-down circuit including:
a buffer circuit configured to receive a second regulated voltage signal at a power supply node that is lower than the supply voltage signal and generate inverted signals using the second regulated voltage signal and the clock signal, the clock signal generator coupled between the first transistor and the step-down circuit;
a second transistor coupled between the power supply node and the application node; and
a third transistor coupled between the power supply node and the application node; and
a charge pump circuit coupled between the step-down circuit and the first transistor, the buffer circuit coupled between the charge pump circuit and the clock signal generator, the charge pump circuit being controlled by the inverted signals and configured to supply a control signal to a gate of the first transistor,
the second transistor configured to be controlled by a reference voltage, and the third transistor being configured to be controlled by the control signal.
19 . A regulator, comprising:
a first transistor coupling an application node of a first supply voltage to an output node of the regulator to supply a first regulated voltage;
a feedback loop supplying a control signal to the first transistor, the feedback loop including:
a first charge pump circuit;
a first control signal generator for the first charge pump circuit; and
a first comparator circuit configured to compare the first regulated voltage to a first reference voltage, the first charge pump circuit is enabled or disabled in accordance with the comparison between the first regulated voltage and the first reference voltage;
a step-down circuit coupled between the first control signal generator and the first charge pump circuit;
a second charge pump circuit configured to supply the control signal to the first transistor in case the first charge pump circuit is disabled;
a second comparator circuit configured to compare the first regulated voltage with a second reference voltage lower than the first reference voltage; and
a second control signal generator, the second charge pump circuit being controlled by the second control signal generator in accordance with the comparison between the first regulated voltage and the second reference voltage.
20 . The regulator according to claim 19 , wherein the step-down circuit includes a power supply node, and the output node is coupled to the power supply node of the step-down circuit.