IP Library Granted Patent US 12,405,855
Granted Patent B2
US 12,405,855 · App. 18/609,039 · Granted Sep 2, 2025

Storage device and a method of error processing thereof

Inventors: Masanori Takada (Tokyo, JP); Katsuya Tanaka (Tokyo, JP)
Assignee: HITACHI VANTARA, LTD.
G06F11/1064G06F12/0871G06F12/126
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,405,855
App. No.
18/609,039
Filed
Mar 19, 2024
Granted
Sep 2, 2025
Kind
B2
Art Unit
2112
USPC
714/764
Abstract

In a storage device including a plurality of controllers for controlling data reading and writing operations with respect to at least one host computer, each of the controllers includes: a cache region to which a plurality of management units capable of temporarily storing the data are allocated in accordance with the data reading and writing operations; and a control unit for controlling the data reading and writing operations, and when an error occurs, the control unit determines whether or not an occurrence position of the error is in the cache region, and when it is determined that the occurrence position is in the cache region, the control unit excludes, among the plural management units, a specific management unit that contains the occurrence position from an allocation target in the cache region, to control the data reading and writing operations using remaining management units in the plural management units.

Claims (20)

1. A storage device comprising a plurality of controllers for controlling data reading and writing operations with respect to at least one host computer, wherein

each of the controllers includes:

a cache region to which a plurality of management units capable of temporarily storing the data are allocated in accordance with the data reading and writing operations; and

a control unit for controlling the data reading and writing operations, and when an error occurs, the control unit determines whether or not an occurrence position of the error is in the cache region, and when it is determined that the occurrence position is in the cache region, the control unit excludes, among the plural management units, a specific management unit that contains the occurrence position from an allocation target in the cache region, to control the data reading and writing operations using remaining management units in the plural management units.

2. The storage device according to claim 1 , wherein the control unit determines whether or not the error is correctable, and, when the error is not correctable, the control unit excludes the specific management unit from the allocation target.

3. The storage device according to claim 2 , wherein each of the controllers includes a usage exclusion list for managing identification information indicating the specific management unit excluded from the allocation target.

4. The storage device according to claim 1 , wherein each of the controllers includes a cache directory for managing a correlation between plural storage units in a volume which stores the data, and the plural management units in the cache region which stores the data.

5. The storage device according to claim 1 , wherein each of the controllers includes a hardware failure management table for managing the occurrence position in the cache region.

6. The storage device according to claim 1 , wherein each of the controllers includes a replacement target management table for managing a cache as a replacement target, that includes the cache region having the specific management unit excluded from the allocation target.

7. An error processing method for a storage device having a plurality of controllers each provided with a control unit for controlling data reading and writing operations with respect to at least one host computer, the error processing method comprising:

a management unit allocation step for causing the control unit to allocate a plurality of management units capable of temporarily storing the data to each cache region of the controllers in accordance with the data reading and writing operations;

a determination step for causing the control unit to determine, when an error occurs, whether or not an occurrence position of the error is in the cache region; and

a control step for causing the control unit, when it is determined that the occurrence position is in the cache region, to exclude a specific management unit including the occurrence position among the management units from the allocation target in the cache region, and to control the data reading and writing operations using remaining management units in the plural management units.

8. The error processing method according to claim 7 , wherein in the management unit allocation step, the control unit determines whether or not the error is correctable, and, when the error is not correctable, excludes the specific management unit from the allocation target.

9. The error processing method according to claim 8 , wherein

each of the controllers includes a usage exclusion list for managing identification information indicating the specific management unit excluded from the allocation target, and

in the control step, the control unit controls the data reading and writing operations so as not to use the specific management unit corresponding to identification information managed in the usage exclusion list.

10. The error processing method according to claim 7 , wherein

each of the controllers includes a cache directory for managing a correlation between a plurality of storage units in a volume which stores the data, and the plural management units in the cache region which stores the data, and

in the control step, the control unit identifies a predetermined storage unit in the volume corresponding to a predetermined management unit in the cache region with reference to the cache directory.

Assignments (2)
MERGER Recorded Aug 26, 2024
From: HITACHI, LTD.
To: HITACHI VANTARA, LTD.
Reel/Frame 068393/0234 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2024
From: TAKADA, MASANORI; TANAKA, KATSUYA
To: HITACHI, LTD.
Reel/Frame 066818/0304 →
Priority Claims (1)
JP 2023-185681 · Oct 30, 2023 · national
Continuity (1)
Related Publication 20250138943A1 · May 1, 2025
References Cited (9)
US 12094503B1 · Guo · 2024 [cited by examiner]
US 20040123068A1 · Hashimoto · 2004 [cited by applicant]
US 20090006705A1 · Bartley · 2009 [cited by examiner]
US 20120144252A1 · Takada · 2012 [cited by examiner]
US 20160048425A1 · Kim · 2016 [cited by examiner]
US 20190303236A1 · Ellis · 2019 [cited by examiner]
US 20240069997A1 · Bukhari · 2024 [cited by examiner]
US 20240420735A1 · Galbraith · 2024 [cited by examiner]
JP 2004199420A · 2004 [cited by applicant]
Cited By (1)
US 12,596,688