Integrated circuit chips for a phased array system including programmable on-chip element swapping, channel swapping, and/or phase rotation circuitry
Exemplary embodiments include RF integrated circuit (RFIC) chips including programmable on-chip element swapping circuitry, channel swapping circuitry, and/or phase rotation circuitry to allow a common software implementation or parameter computation to be used across multiple products having different arrangements and orientations of RFICs and elements.
1 . A radio frequency integrated circuit (RFIC) chip comprising:
a first common RF port;
a second common RF port;
at least one element interface circuit, wherein each element interface circuit is coupled to the first common RF port or the second common RF port, and wherein each element interface circuit comprises:
a first element interface circuit comprising a first 180 degree phase shifter; and
a second element interface circuit comprising a second 180 degree phase shifter;
programmable channel swapping circuitry configured to selectively switch between a first channel configuration and a second channel configuration based on a channel swap parameter,
wherein in the first channel configuration the first common RF port is coupled to the first element interface circuit of each element interface circuit and the second common RF port is coupled to the second element interface circuit of each element interface circuit, and
wherein in the second channel configuration the first common RF port is coupled to the second element interface circuit of each element interface circuit and the second common RF port is coupled to the first element interface circuit of each element interface circuit; and
programmable phase rotation circuitry configured to selectively enable or disable the 180 degree phase shifter of the first element interface circuit and the second element interface circuit of each of the at least one element interface circuit based on a corresponding element rotation parameter.
2 . The RFIC chip of claim 1 , wherein the programmable channel swapping circuitry comprises switching circuitry having a first input coupled to the first common RF port, a second input coupled to the second common RF port, a first output coupled to the first element interface circuit of each element interface circuit, a second output coupled to the second element interface circuit of each element interface circuit, and a switch for selectively switching between a first switch configuration and a second switch configuration based on the channel swap parameter,
the first switch configuration corresponding to the first channel configuration and coupling the first input to the first output and coupling the second input to the second output, the second switch configuration corresponding to the second channel configuration and coupling the first input to the second output and coupling the second input to the first output.
3 . The RFIC chip of claim 1 , further comprising:
at least one memory storing, for each element interface circuit, a first set of gain and phase parameters and a second set of gain and phase parameters; and
parameter swapping circuitry configured to selectively switch each element interface circuit between a first parameter configuration corresponding to the first channel configuration and a second parameter configuration corresponding to the second channel configuration based on the channel swap parameter, the first parameter configuration providing the first set of gain and phase parameters to the first element interface circuit and providing the second set of gain and phase parameters to the second element interface circuit, the second parameter configuration providing the first set of gain and phase parameters to the second element interface circuit and providing the second set of gain and phase parameters to the first element interface circuit.
4 . The RFIC chip of claim 3 , wherein the parameter swapping circuitry comprises:
first switching circuitry configured to selectively switch the gain parameters; and
second switching circuitry configured to selectively switch the phase parameters.
5 . The RFIC chip of claim 1 , further comprising:
at least one memory storing a set of gain and phase parameters for each element interface circuit including at least a first set of gain and phase parameters for the first element interface circuit and a second set of gain and phase parameters for the second element interface circuit; and
programmable element swapping circuitry configured selectively switch between a first element configuration and a second element configuration based on an element swap parameter, the first element configuration providing the first set of gain and phase parameters to the first element interface circuit and providing the second set of gain and phase parameters to the second element interface circuit, the second element configuration providing the first set of gain and phase parameters to the second element interface circuit and providing the second set of gain and phase parameters to the first element interface circuit.
6 . The RFIC chip of claim 5 , wherein the element swapping circuitry is configured to digitally switch the sets of gain and phase parameters.
7 . The RFIC chip of claim 5 , wherein the programmable element swapping circuitry and the programmable channel swapping circuitry are controlled through a common parameter.
8 . The RFIC chip of claim 7 , wherein the common parameter is an orientation parameter based on an orientation of the RFIC chip relative to a reference orientation.
9 . The RFIC chip of claim 8 , wherein the orientation parameter indicates an angle of rotation from the reference orientation.
10 . A phased array system comprising at least one RFIC chip, wherein the at least one RFIC chip comprises the RFIC chip of claim 1 .
11 . The phased array system of claim 10 , wherein the programmable channel swapping circuitry of the RFIC chip comprises switching circuitry having a first input coupled to the first common RF port, a second input coupled to the second common RF port, a first output coupled to the first element interface circuit of each element interface circuit, a second output coupled to the second element interface circuit of each element interface circuit, and a switch for selectively switching between a first switch configuration and a second switch configuration based on the channel swap parameter, the first switch configuration corresponding to the first channel configuration and coupling the first input to the first output and coupling the second input to the second output, the second switch configuration corresponding to the second channel configuration and coupling the first input to the second output and coupling the second input to the first output.
12 . The phased array system of claim 10 , wherein the RFIC chip further comprises:
at least one memory storing, for each element interface circuit, a first set of gain and phase parameters and a second set of gain and phase parameters; and
parameter swapping circuitry configured to selectively switch each element interface circuit between a first parameter configuration corresponding to the first channel configuration and a second parameter configuration corresponding to the second channel configuration based on the channel swap parameter, the first parameter configuration providing the first set of parameters to the first element interface circuit and providing the second set of parameters to the second element interface circuit, the second parameter configuration providing the first set of parameters to the second element interface circuit and providing the second set of parameters to the first element interface circuit.
13 . The phased array system of claim 12 , wherein the parameter swapping circuitry comprises:
first switching circuitry configured to selectively switch the gain parameters; and
second switching circuitry configured to selectively switch the phase parameters.
14 . The phased array system of claim 10 , wherein the at least one element interface circuit of the RFIC chip comprises a plurality of element interface circuits.
15 . The phased array system of claim 14 , wherein the RFIC chip further comprises:
at least one memory storing a set of gain and phase parameters for each element interface circuit including at least a first set of gain and phase parameters for a first element interface circuit and a second set of gain and phase parameters for a second element interface circuit; and
programmable element swapping circuitry configured selectively switch between a first element configuration and a second element configuration based on an element swap parameter, the first element configuration providing the first set of gain and phase parameters to the first element interface circuit and providing the second set of gain and phase parameters to the second element interface circuit, the second element configuration providing the first set of gain and phase parameters to the second element interface circuit and providing the second set of gain and phase parameters to the first element interface circuit.
16 . The phased array system of claim 15 , wherein the element swapping circuitry is configured to digitally switch the sets of parameters.
17 . The phased array system of claim 15 , wherein the element swapping circuitry and the channel swapping circuitry are controlled through a common parameter.
18 . The phased array system of claim 17 , wherein the common parameter is an orientation parameter based on an orientation of the RFIC chip relative to a reference orientation.
19 . The phased array system of claim 18 , wherein the orientation parameter indicates an angle of rotation from the reference orientation.
20 . A wireless communication system comprising:
a radio frequency integrated circuit (RFIC) chip comprising:
a first common RF port;
a second common RF port;
at least one element interface circuit, wherein each element interface circuit is coupled to the first common RF port or the second common RF port, and wherein each element interface circuit comprises:
a first element interface circuit comprising a first 180 degree phase shifter; and
a second element interface circuit comprising a second 180 degree phase shifter;
programmable channel swapping circuitry configured to selectively switch between a first channel configuration and a second channel configuration based on a channel swap parameter,
wherein in the first channel configuration the first common RF port is coupled to the first element interface circuit of each element interface circuit and the second common RF port is coupled to the second element interface circuit of each element interface circuit, and
wherein in the second channel configuration the first common RF port is coupled to the second element interface circuit of each element interface circuit and the second common RF port is coupled to the first element interface circuit of each element interface circuit; and
programmable phase rotation circuitry configured to selectively enable or disable the 180 degree phase shifter of the first element interface circuit and the second element interface circuit of each of the at least one element interface circuit based on a corresponding element rotation parameter.