Array substrate and method of manufacturing the same, and display panel
The present disclosure provides an array substrate and a method of manufacturing the same and a display panel, which belongs to the field of display technologies. The method of manufacturing the array substrate comprises: providing a base substrate; forming a drive circuit layer on the base substrate, wherein the drive circuit layer includes a switching transistor; forming an insulating material layer on one side of the drive circuit layer distal to the base substrate, wherein the insulating material layer has a connection via-hole exposing at least a part region of a drain electrode of the switching transistor; and forming an electrode layer on one side of the insulating material layer distal to the base substrate, wherein a surface of the electrode layer distal to the base substrate has groove structures extending to the connection via-hole.
1. An array substrate, comprising:
a base substrate;
a drive circuit layer, disposed on one side of the base substrate and comprising a switching transistor;
an insulating material layer, disposed on one side of the drive circuit layer distal to the base substrate, and having a connection via-hole exposing at least a part region of a drain electrode of the switching transistor; and
an electrode layer, disposed on one side of the insulating material layer distal to the base substrate, wherein a surface of the electrode layer distal to the base substrate has at least one groove structure extending to the connection via-hole;
wherein the electrode layer comprises a second electrode layer; and
an opening of the connection via-hole is in a rectangular shape, a size of the opening of the connection via-hole close to the base substrate in an extension direction of a scan line in the drive circuit layer is 10-12 microns, and the size of the opening of the connection via-hole close to the base substrate in an extension direction of a data line in the drive circuit layer is 6.5-7.5 microns, and
the second electrode layer has a common electrode and covers the connection via-hole, the second electrode layer comprises a plurality of strip sub-electrodes, slits located among the strip sub-electrodes, and drainage grooves serving as the groove structures, wherein the strip sub-electrode has a width of 2.5 to 3.5 microns and the slit has a width of 3.0 to 5.0 microns, the drainage grooves are in communication with the slits and extend to the connection via-hole, a length of a part of the drainage groove within the connection via-hole is 6.0 to 6.5 microns, and the drainage groove and the communicated slit have a same width and extension direction.
2. The array substrate according to claim 1 , wherein the electrode layer further comprises a first electrode layer and an insulating dielectric layer; and wherein the first electrode layer, the insulating dielectric layer, and the second electrode layer are sequentially laminated on one side of the insulating material layer distal to the base substrate.
3. The array substrate according to claim 1 , wherein the insulating material layer comprises an organic insulating layer, and the organic insulating layer has the connection via-hole exposing at least the part region of the drain electrode of the switching transistor.
4. The array substrate according to claim 2 , wherein
the second electrode layer has a plurality of drainage grooves extending to the connection via-hole, and the drainage grooves serves as the groove structures of the electrode layer;
or, the insulating dielectric layer has a plurality of drainage grooves extending to the connection via-hole, the second electrode layer is bent inwardly into the drainage groove, to form the groove structure, and an orthographic projection of the groove structure on the insulating dielectric layer is located within the drainage groove;
or, the first electrode layer has a plurality of drainage grooves extending to the connection via-hole, the insulating dielectric layer and the second electrode layer cover a bottom and side walls of the drainage groove, to form the groove structure, and an orthographic projection of the groove structure on the first electrode layer is located within the drainage groove.
5. The array substrate according to claim 1 , wherein a depth of the groove structure is equal to a thickness of the second electrode layer.
6. The array substrate according to claim 1 , wherein a part of the groove structure within the connection via-hole is located on a side wall of the connection via-hole.
7. A display panel, comprising the array substrate of claim 1 .
8. An array substrate, comprising:
a base substrate;
a drive circuit layer, disposed on one side of the base substrate and comprising a switching transistor;
an insulating material layer, disposed on one side of the drive circuit layer distal to the base substrate, and having a connection via-hole exposing at least a part region of a drain electrode of the switching transistor; and
an electrode layer, disposed on one side of the insulating material layer distal to the base substrate, wherein a surface of the electrode layer distal to the base substrate has at least one groove structure extending to the connection via-hole;
wherein the electrode layer comprises a second electrode layer; and
an opening of the connection via-hole is in a circular shape and the opening close to the base substrate has a diameter of 7 to 8 microns, and
the second electrode layer has a common electrode and covers the connection via-hole, the second electrode layer comprises a plurality of strip sub-electrodes, slits located among the strip sub-electrodes, and drainage grooves serving as the groove structures, wherein the strip sub-electrode has a width of 2.5 to 3.5 microns and the slit has a width of 3.0 to 5.0 microns, the drainage grooves are in communication with the slits and extend to the connection via-hole, a length of a part of the drainage groove within the connection via-hole is 0.8 to 1.2 microns, and the drainage groove and the communicated slit have a same width and extension direction.
9. The array substrate according to claim 8 , wherein the electrode layer further comprises a first electrode layer and an insulating dielectric layer; and wherein the first electrode layer, the insulating dielectric layer, and the second electrode layer are sequentially laminated on one side of the insulating material layer distal to the base substrate.
10. The array substrate according to claim 8 , wherein the insulating material layer comprises an organic insulating layer, and the organic insulating layer has the connection via-hole exposing at least the part region of the drain electrode of the switching transistor.
11. The array substrate according to claim 9 , wherein
the second electrode layer has a plurality of drainage grooves extending to the connection via-hole, and the drainage grooves serves as the groove structures of the electrode layer;
or, the insulating dielectric layer has a plurality of drainage grooves extending to the connection via-hole, the second electrode layer is bent inwardly into the drainage groove, to form the groove structure, and an orthographic projection of the groove structure on the insulating dielectric layer is located within the drainage groove;
or, the first electrode layer has a plurality of drainage grooves extending to the connection via-hole, the insulating dielectric layer and the second electrode layer cover a bottom and side walls of the drainage groove, to form the groove structure, and an orthographic projection of the groove structure on the first electrode layer is located within the drainage groove.
12. The array substrate according to claim 8 , wherein a depth of the groove structure is equal to a thickness of the second electrode layer.
13. The array substrate according to claim 8 , wherein a part of the groove structure within the connection via-hole is located on a side wall of the connection via-hole.
14. An array substrate, comprising:
a base substrate;
a drive circuit layer, disposed on one side of the base substrate and comprising a switching transistor;
an insulating material layer, disposed on one side of the drive circuit layer distal to the base substrate, and having a connection via-hole exposing at least a part region of a drain electrode of the switching transistor; and
an electrode layer, disposed on one side of the insulating material layer distal to the base substrate, wherein a surface of the electrode layer distal to the base substrate has at least one groove structure extending to the connection via-hole;
wherein the electrode layer comprises a second electrode layer; and
an opening of the connection via-hole is in a rectangular shape, a size of the opening of the connection via-hole close to the base substrate in an extension direction of a scan line in the drive circuit layer is 11.5˜13.5 microns, the size of the opening of the connection via-hole close to the base substrate in an extension direction of a data line in the drive circuit layer is 10 to 12 microns, and the size of the connection via-hole in the extension direction of the scan line is greater than the size of the connection via-hole in the extension direction of the data line, and
the second electrode layer has a pixel electrode and covers the connection via-hole, the second electrode layer comprises a plurality of strip sub-electrodes, slits located among the strip sub-electrodes, and drainage grooves serving as the groove structures, wherein the strip sub-electrode has a width of 2.5 to 3.5 microns and the slit has a width of 3.0 to 5.0 microns, the drainage grooves are in communication with the slits and extend to the connection via-hole, a length of a part of the drainage groove within the connection via-hole is 1.5 to 2.5 microns, and the drainage groove and the communicated slit have a same width and extension direction.
15. The array substrate according to claim 14 , wherein the electrode layer further comprises a first electrode layer and an insulating dielectric layer; and wherein the first electrode layer, the insulating dielectric layer, and the second electrode layer are sequentially laminated on one side of the insulating material layer distal to the base substrate.
16. The array substrate according to claim 14 , wherein the insulating material layer comprises an organic insulating layer, and the organic insulating layer has the connection via-hole exposing at least the part region of the drain electrode of the switching transistor.
17. The array substrate according to claim 15 , wherein
the second electrode layer has a plurality of drainage grooves extending to the connection via-hole, and the drainage grooves serves as the groove structures of the electrode layer;
or, the insulating dielectric layer has a plurality of drainage grooves extending to the connection via-hole, the second electrode layer is bent inwardly into the drainage groove, to form the groove structure, and an orthographic projection of the groove structure on the insulating dielectric layer is located within the drainage groove;
or, the first electrode layer has a plurality of drainage grooves extending to the connection via-hole, the insulating dielectric layer and the second electrode layer cover a bottom and side walls of the drainage groove, to form the groove structure, and an orthographic projection of the groove structure on the first electrode layer is located within the drainage groove.
18. The array substrate according to claim 14 , wherein a depth of the groove structure is equal to a thickness of the second electrode layer.
19. The array substrate according to claim 14 , wherein a part of the groove structure within the connection via-hole is located on a side wall of the connection via-hole.