Single clock delay step in multi-stage switched-capacitor delays
View Patent ↗A programmable delay device providing a delay resolution of less than 1 ns and a maximum delay of >100 ns over a broad bandwidth is disclosed. The device includes an input stage with M sampling switched capacitor elements, reducing the sampling rate by M. The device includes a programmable delay stage with M programmable switched capacitor banks, each bank having N delay switched capacitor storage elements. The programmable delay stage includes a total of M×N delay switched capacitor storage elements, reducing the sampling rate by M×N. This reduced sampling rate permits smaller sampling switches, with reduced leakage current and longer programmable delay times. The device includes an output reconstruction stage that reconstructs a delayed version of the input signal by combining signals from the programmable delay stage. The sampling clocks for the input and output reconstruction stages are independent, allowing a delay resolution corresponding to the sampling rate.
1 . A programmable delay device comprising:
an input sampling stage adapted to receive an input sampling clock at a frequency F S and an input RF signal, the input sampling stage including M sampling switched capacitor storage elements, the M sampling switched capacitor storage elements adapted to sequentially sample and hold a corresponding portion of the input RF signal, the thus sampled and held portions of the input RF signal being input sampled signals;
a programmable delay stage including M programmable switched capacitor banks, each programmable switched capacitor bank including N delay switched capacitor storage elements, each delay switched capacitor storage element adapted to sample and hold a corresponding time interleaved portion of a corresponding input sampled signal, the thus sampled and held signals being delay sampled switched signals;
a programmable enable delay circuit adapted to receive a desired fine delay value and the input sampling clock, the programmable enable delay circuit adapted to generate an enable output signal with a time delay based upon the desired fine delay value, an incremental fine delay value corresponding to 1/F S , the programmable enable delay circuit adapted to output the enable output signal and the input sampling clock as an output clock;
an enable timing circuit adapted to receive a desired coarse delay value, the enable output signal, and the output clock, the enable timing circuit including a digital counter, the digital counter adapted to count to the desired coarse delay value, upon reaching the desired coarse delay value the enable timing circuit is adapted to output a corresponding output reconstruction clock, an incremental coarse delay value corresponding to M/F S ; and
an output reconstruction stage including M output reconstruction switches, each output reconstruction switch coupled to a corresponding delay output switch, each output reconstruction switch adapted to output a corresponding time interleaved delay sampled switched signal based upon the output reconstruction clock, the thus output time interleaved delay sampled switched signals being output reconstruction signals, the output reconstruction stage adapted to output the output reconstruction signals in a sequential manner thereby generating a reconstructed output RF signal.
2 . The programmable delay device of claim 1 , further comprising a selectable clock divider adapted to receive an input clock, to divide the input clock by P, and to output the thus generated divide-by-P clock to the input sampling stage as the input sampling clock.
3 . The programmable delay device of claim 1 , wherein M is equal to or greater than 4.
4 . The programmable delay device of claim 1 , wherein each sampling switched capacitor storage element includes:
an input sampling capacitor adapted to hold a corresponding input sampled signal; and
an input sampling switch adapted to sequentially couple the input RF signal to the input sampling capacitor.
5 . The programmable delay device of claim 1 , wherein N is equal to or greater than 2.
6 . The programmable delay device of claim 1 , wherein each delay switched capacitor storage element includes:
a switched bank sampling capacitor adapted to hold a corresponding delay sampled switched signal; and
an input switched bank switch adapted to couple a corresponding input sampled signal to the switched bank sampling capacitor in a time interleaved manner.
7 . The programmable delay device of claim 1 , wherein the input sampling stage further includes M intervening buffers, each intervening buffer adapted to couple a corresponding sampling switched capacitor storage element to a corresponding programmable switched capacitor bank.
8 . The programmable delay device of claim 1 , wherein the programmable delay stage further includes M×N delay buffers, each delay buffer adapted to couple a corresponding delay switched capacitor storage element to a corresponding delay output switch.
9 . The programmable delay device of claim 1 , wherein the programmable enable delay circuit includes a plurality of flip-flops adapted to generate the enable output signal in accordance with the desired fine delay value, the enable output signal including an inherent delay due to one or more of the plurality of flip-flops.
10 . The programmable delay device of claim 9 , wherein the programmable enable delay circuit further includes one or more second flip-flops adapted to generate an enable input signal, the enable input signal including a second inherent delay due to the one or more second flip-flops, the second inherent delay due to the one or more second flip-flops substantially equal to the inherent delay due to the one or more of the plurality of flip-flops, the programmable enable delay circuit adapted to output the enable input signal to the input sampling stage.
11 . The programmable delay device of claim 1 ,
wherein the programmable enable delay circuit is further adapted to output the enable output signal to the input sampling stage; and
wherein the input sampling stage and the enable timing circuit start in different initialization states corresponding to the desired fine delay value.
12 . The programmable delay device of claim 1 , wherein the output reconstruction stage further includes M self-biased inverter load, each self-biased inverter load adapted to couple a corresponding delay output switch to a corresponding output reconstruction switch.
13 . The programmable delay device of claim 1 :
wherein the input sampling stage further includes an input divide-by-M clock adapted to receive the input sampling clock, to divide the input sampling clock by M, and to output M thus generated input divide-by-M clocks;
wherein the programmable delay stage further includes M input divide-by-N clocks, each input divide-by-N clock adapted to receive a corresponding input divide-by-M clock, to divide the corresponding input divide-by-M clock by N, and to output N thus generated input divide-by-N clocks;
wherein each sampling switched capacitor storage element is adapted to be operated by a corresponding input divide-by-M clock; and
wherein each delay switched capacitor storage element is adapted to be operated by a corresponding input divide-by-N clock.
14 . The programmable delay device of claim 13 , wherein the input sampling stage further includes an input pulse extend clock adapted to receive the M input divide-by-M clocks, to lengthen a pulse length of each input divide-by-M clock, and to output M thus generated input pulse extended clocks to the M input divide-by-N clocks as corresponding input divide-by-M clocks.
15 . The programmable delay device of claim 13 ,
wherein the enable timing circuit further includes an output divide-by-M clock adapted to receive the output clock, to divide the output clock by M, and to output M thus generated output divide-by-M clocks;
wherein the programmable delay stage further includes M output divide-by-N clocks, each output divide-by-N clock adapted to receive a corresponding output divide-by-M clock, to divide the corresponding output divide-by-M clock by N, and to output N thus generated output divide-by-N clocks;
wherein each output reconstruction switch is adapted to be operated by a corresponding output divide-by-M clock; and
wherein each delay output switch is adapted to be operated by a corresponding output divide-by-N clock.
16 . The programmable delay device of claim 13 , wherein the enable timing circuit further includes an output pulse extend clock adapted to receive the M output divide-by-M clocks, to lengthen a pulse length of each output divide-by-M clock, and to output M thus generated output pulse extended clocks as corresponding output divide-by-M clocks.
17 . The programmable delay device of claim 1 further comprising a serial programming interface adapted to receive the desired fine delay value and the desired coarse delay value from an external programming source, to output the desired fine delay value to the programmable enable delay circuit, and to output the desired coarse delay value to the enable timing circuit.
18 . The programmable delay device of claim 1 , wherein at least a portion of the programmable delay device is implemented with CMOS circuitry.
19 . The programmable delay device of claim 1 , wherein at least a portion of the programmable delay device is implemented in either a single-ended configuration or a differential configuration.
20 . The programmable delay device of claim 1 , wherein the programmable delay device has an area efficiency of greater than 100 ns/mm 2 .