IP Library › Granted Patent US 12,620,889
Granted Patent B2
US 12,620,889 · App. 18/620,256 · Granted May 5, 2026

BOOT UVLO detection scheme for high voltage applications

Inventors: Jairo Olivares (Richardson, TX); Alejandro Vera (Wylie, TX); Mitchell Levine (Celina, TX)
Assignees: NEXPERIA B.V; Nexperia Technology (Shanghai) Ltd.
H02M1/32H02M1/088H02M3/01H02M3/158
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Quick Facts
Patent No.
US 12,620,889
App. No.
18/620,256
Granted
May 5, 2026
Kind
B2
Abstract

A buck converter including a high-side switch, a low-side switch and a bootstrap (BOOT), under-voltage lockout (UVLO) circuit. The BOOT UVLO circuit includes a BOOT UVLO detection element configured to compare a BOOT voltage with a switch node (SW) voltage to determine an occurrence of a BOOT UVLO event. The BOOT UVLO detection element is configured to output an UVLO signal (UVLO_Z), in case of the BOOT UVLO event. The BOOT UVLO circuit further includes a logic gate configured to receive the UVLO_Z and a high-side ON, (HSON) signal, the HSON signal is for controlling a switching of the high-side switch. The logic gate is configured to negate the HSON signal when receiving the UVLO_Z while the HSON signal is ON, to thereby immediately switch OFF the high-side switch when the HSON signal is ON.

Claims (48)

1 . A buck converter comprising:

a high-side switch;

a low-side switch; and

a bootstrap (BOOT) under-voltage lockout (UVLO) circuit,

wherein the BOOT UVLO circuit comprises:

a BOOT UVLO detection element configured to compare a BOOT voltage with a switch node (SW) voltage to determine an occurrence of a BOOT UVLO event, wherein the BOOT UVLO detection element is configured to output an UVLO signal (UVLO_Z), in case of the BOOT UVLO event; and

a logic gate configured to receive the UVLO_Z and a high-side ON (HSON), signal;

wherein the HSON signal is for controlling a switching of the high-side switch; and

wherein the logic gate is configured to negate the HSON signal when receiving the UVLO_Z while the HSON signal is ON, to thereby switch OFF the high-side switch when the HSON signal is ON.

2 . The buck converter according to claim 1 , further comprising:

a gate driver circuit,

wherein the logic gate has an output that is an input to the gate driver circuit, and

wherein the gate driver circuit has an output that is an input to a gate of the high-side switch.

3 . The buck converter according to claim 1 , wherein the high-side switch has a source that is connected to the BOOT UVLO circuit via the SW.

4 . The buck converter according to claim 1 ,

wherein the high-side switch has a gate that is connected to an input of a high-side (HS) gate-source voltage (V GS ) detection element configured to detect whether the high-side switch is turned ON or OFF based on the V GS ; and

wherein the V GS detection element is configured to output a high-side OK (HSOK) signal indicative of the high-side switch being turned ON or OFF.

5 . The buck converter according to claim 2 , wherein the high-side switch has a source that is connected to the BOOT UVLO circuit via the SW.

6 . The buck converter according to claim 4 , further comprising a logic element, wherein the logic element is configured to:

detect, based on the HSOK signal, that the high-side switch is turned OFF while the HSON signal is ON; and

start a BOOT refresh algorithm when it is detected that the high-side switch is turned OFF while the HSON signal is ON.

7 . The buck converter according to claim 6 , wherein the BOOT refresh algorithm is configured to sequentially:

switch ON the low-side switch using a low-side ON (LSON) signal;

try to switch ON the high-side switch using the HSON signal; and

determine, based on the HSOK signal, whether the high-side switch is turned ON.

8 . The buck converter according to claim 7 , wherein the BOOT refresh algorithm is configured to repeat the sequential steps until it is determined, based on the HSOK signal, that the high-side switch is turned ON.

9 . The buck converter according to claim 7 , wherein the BOOT refresh algorithm is configured to:

apply a first time delay after switching ON the low-side switch using the LSON signal; and

apply a second time delay after trying to switch ON the high-side switch using the HSON signal.

10 . The buck converter according to claim 8 , wherein the BOOT refresh algorithm is configured to:

apply a first time delay after switching ON the low-side switch using the LSON signal; and

apply a second time delay after trying to switch ON the high-side switch using the HSON signal.

11 . The buck converter according to claim 10 , wherein the first time delay is about 300 ns and the second time delay is about 100 ns.

12 . A method of detecting a bootstrap (BOOT), under-voltage lockout (UVLO), event in a buck converter, the method comprising the steps of:

detecting, based on a high-side OK (HSOK) signal indicative of a high-side switch of the buck converter being turned ON or OFF, that the high-side switch is turned OFF while a high-side ON (HSON) signal for controlling the switching of the high-side switch is ON; and

starting a BOOT refresh algorithm when it is detected that the high-side switch is turned OFF while the HSON signal is ON.

13 . The method according to claim 12 , wherein the BOOT refresh algorithm comprises sequentially:

switching ON a low-side switch of the buck converter using a low-side ON (LSON) signal;

trying to switch ON the high-side switch using the HSON signal; and

determining, based on the HSOK signal, whether the high-side switch is turned ON.

14 . The method according to claim 13 , wherein the BOOT refresh algorithm further comprises repeating the sequential steps until it is determined, based on the HSOK signal, that the high-side switch is turned ON.

15 . The method according to claim 13 , wherein the BOOT refresh algorithm further comprises:

applying a first time delay after switching ON the low-side switch using the LSON signal; and

applying a second time delay after trying to switch ON the high-side switch using the HSON signal.

16 . The method according to claim 14 , wherein the BOOT refresh algorithm further comprises:

applying a first time delay after switching ON the low-side switch using the LSON signal; and

applying a second time delay after trying to switch ON the high-side switch using the HSON signal.

17 . The method according to claim 15 , wherein the first time delay is about 300 ns and the second time delay is about 100 ns.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2024
From: OLIVARES, JAIRO; VERA, ALEJANDRO; LEVINE, MITCHELL
To: NEXPERIA B.V.
Reel/Frame 066945/0134 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2024
From: OLIVARES, JAIRO; VERA, ALEJANDRO; LEVINE, MITCHELL
To: NEXPERIA TECHNOLOGY (SHANGHAI) LTD.
Reel/Frame 066945/0305 →
Continuity (1)
Related Publication 20250309752A1 · Oct 2, 2025
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