Scaled one transistor two resistor (1T 2R) memory
A semiconductor structure includes a selection transistor having a first drain-source terminal, a second drain-source terminal, at least one channel region between the first and second source-drain terminals, and a gate adjacent the at least one channel region. A first vertical contact structure is connected to the first drain-source terminal. A second vertical contact structure is connected to the second drain-source terminal. A first resistive memory cell has a lower electrode coupled to the second vertical contact structure and has an upper electrode. A third vertical contact structure is connected to the upper electrode of the first resistive memory cell. A second resistive memory cell has an upper electrode coupled to the second vertical contact structure and has a lower electrode. A fourth vertical contact structure is connected to the lower electrode of the second resistive memory cell.
1 . A semiconductor structure comprising:
a selection transistor having a first drain-source terminal, a second drain-source terminal, at least one channel region between the first drain-source terminal and the second drain-source terminal, and a gate adjacent the at least one channel region;
a first vertical contact structure connected to the first drain-source terminal;
a second vertical contact structure connected to the second drain-source terminal, wherein the second vertical contact structure comprises a via extending to a lateral portion of a lower electrode of a first resistive memory cell that extends away from the first vertical contact structure;
the first resistive memory cell having the lower electrode coupled to the second vertical contact structure and having an upper electrode;
a third vertical contact structure connected to the upper electrode of the first resistive memory cell;
a second resistive memory cell having an upper electrode and a lower electrode, the lower electrode of the second resistive memory cell coupled to the first vertical contact structure; and
a fourth vertical contact structure connected to the upper electrode of the second resistive memory cell.
2 . The semiconductor structure of claim 1 , wherein the first and second resistive memory cells comprise resistive random-access memory (ReRAM).
3 . The semiconductor structure of claim 1 , wherein the first and second resistive memory cells comprise phase-change random-access memory (PCRAM).
4 . The semiconductor structure of claim 1 , wherein the first and second resistive memory cells comprise ferroelectric random-access memory (FERAM).
5 . The semiconductor structure of claim 1 , wherein the first and second resistive memory cells comprise magnetoresistive random-access memory (MRAM).
6 . The semiconductor structure of claim 1 , wherein the first resistive memory cell and the second resistive memory cell each include a memory switching material between the upper and lower electrodes.
7 . The semiconductor structure of claim 6 , wherein the first resistive memory cell and the second resistive memory cell each further include a bipolar diode.
8 . The semiconductor structure of claim 7 , wherein the bipolar diodes include ovonic threshold switching (OTS) devices.
9 . The semiconductor structure of claim 1 , wherein the first vertical contact structure comprises a first via and a second via extending to a metal line at an outward metal level.
10 . The semiconductor structure of claim 9 , wherein the third vertical contact structure includes a via extending to a second metal line at an inward metal level and a lateral portion of the upper electrode of the first resistive memory cell that extends towards the first vertical contact structure.
11 . The semiconductor structure of claim 10 , wherein:
the first via and the second via of the first vertical contact structure taper from wider upper ends to narrower lower ends;
the via of the second vertical contact structure tapers from a wider upper end to a narrower lower end; and
the via of the third vertical contact structure tapers from a wider upper end to a narrower lower end.
12 . The semiconductor structure of claim 1 , wherein:
the selection transistor comprises a first selection transistor;
the third vertical contact structure comprises a shared contact structure; and
the semiconductor structure further comprises:
a second selection transistor having a first drain-source terminal, a second drain-source terminal, at least one channel region between the first drain-source terminal and the second drain-source terminal, and a gate adjacent the at least one channel region;
a fifth vertical contact structure connected to the first drain-source terminal;
a sixth vertical contact structure connected to the second drain-source terminal;
a third resistive memory cell having a third lower electrode connected to the fifth vertical contact structure and having a third upper electrode coupled to the shared contact structure;
a fourth resistive memory cell having a fourth lower electrode coupled to the sixth vertical contact structure and having a fourth upper electrode; and
a seventh vertical contact structure coupled to the fourth upper electrode of the fourth resistive memory cell.
13 . The semiconductor structure of claim 1 , further comprising:
a third resistive memory cell having a third lower electrode connected to the fourth vertical contact structure and having a third upper electrode;
a fourth resistive memory cell having a fourth upper electrode coupled to the third lower electrode of the third resistive memory cell and having a fourth lower electrode;
a fifth vertical contact structure connected to the third upper electrode of the third resistive memory cell;
a sixth vertical contact structure connected to the fourth lower electrode of the fourth resistive memory cell; and
wherein the third resistive memory cell and the fourth resistive memory cell are located above the first resistive memory cell and the second resistive memory cell.
14 . The semiconductor structure of claim 1 , further comprising peripheral circuitry, a voltage supply, and a controller that are cooperatively configured to selectively energize the gate of the selection transistor, apply a supply voltage to at least one of the first drain-source terminal and the second drain-source terminal, and cause current flow through the at least one channel region.
15 . The semiconductor structure of claim 1 , wherein the selection transistor, the first vertical contact structure, the second vertical contact structure, the first resistive memory cell, the third vertical contact structure, the second resistive memory cell, and the fourth vertical contact structure are repeated in an array, wherein adjacent repetitions of the array share fourth vertical contact structures.
16 . The semiconductor structure of claim 15 , further comprising peripheral circuitry, a voltage supply, and a controller that are cooperatively configured to selectively energize the gate of the selection transistor in one or more repetitions of the array, apply a supply voltage to at least one of the first drain-source terminal, and the second drain-source terminal in the one or more repetitions, and cause current flow through the at least one channel region in the one or more repetitions.
17 . A method of forming a semiconductor structure, comprising:
providing a starting structure including:
a substrate;
a field effect transistor, formed on the substrate, and having a source and a drain with a gate in between;
a source via;
a drain via; and
an inter-layer dielectric (ILD) outward of the substrate and surrounding the field effect transistor, the source via, and the drain via;
forming a first memory cell precursor and a second memory cell precursor on an outer surface of the ILD, the first memory cell precursor and the second memory cell precursor including bottom electrodes, top electrodes, memory switching material intermediate the top electrodes and the bottom electrodes, and a left side liner and a right side liner on the top electrodes and the bottom electrodes;
removing only one of the left side liner and the right side liner from the top electrodes;
removing only the other one of the left liner and the right side liner from the bottom electrodes;
forming a first metal contact on the source via, a second metal contact on the top electrode of the first memory cell precursor, a third metal contact on the bottom electrode of the second memory cell precursor, and a fourth metal contact in a region interconnecting the bottom electrode of the first memory cell precursor, the top electrode of the second memory cell precursor, and the drain via; and
forming vertical metal lines on the first metal contact, the second metal contact, and the third metal contact.
18 . A method of operating a semiconductor structure, comprising:
providing the semiconductor structure, the semiconductor structure comprising:
a selection transistor having a source, a drain, at least one channel region between the source and the drain, and a gate adjacent the at least one channel region;
a first vertical contact structure connected to the source;
a second vertical contact structure connected to the drain, wherein the second vertical contact structure comprises a via extending to a lateral portion of a lower electrode of a first resistive memory cell that extends away from the first vertical contact structure;
the first resistive memory cell having the lower electrode coupled to the second vertical contact structure and having an upper electrode;
a third vertical contact structure connected to the upper electrode of the first resistive memory cell;
a second resistive memory cell having an upper electrode and a lower electrode, the lower electrode of the second resistive memory cell coupled to the first vertical contact structure; and
a fourth vertical contact structure connected to the upper electrode of the second resistive memory cell;
applying a source voltage to the source of the selection transistor;
energizing the gate of the selection transistor;
applying the source voltage to one of the third vertical contact structure and the fourth vertical contact structure; and
applying one of a sensing voltage and a programming voltage at the other one of the third vertical contact structure and the fourth vertical contact structure.
19 . The method of claim 18 , wherein providing the semiconductor structure comprises selecting the first and second resistive memory cells from the group consisting of resistive random-access memory (ReRAM); phase-change random-access memory (PCRAM); ferroelectric random-access memory (FERAM); and magnetoresistive random-access memory (MRAM).
20 . The method of claim 18 , wherein the first resistive memory cells includes a memory switching material between the upper electrode of the first resistive memory cell and the lower electrode of the first resistive memory cell, and wherein the second resistive memory cell includes a memory switching material between the upper electrode of the second resistive memory cell and the lower electrode of the second resistive memory cell.