IP Library › Granted Patent US 12,724,712
Granted Patent B2
US 12,724,712 · App. 18/625,084 · Granted Sep 1, 2026

Scope tree consistency protocol for cache coherence

Inventors: Nicolai Alexander Oswald (San Jose, CA); Evgeny Bolotin (Kenmore, WA); Daniel Joseph Lustig (Woburn, MA); David Nellans (Round Rock, TX); Sean J. Treichler (Piedmont, CA)
Assignee: NVIDIA CORPORATION
G06F12/0815G06F12/0811G06F12/0817G06F12/0842
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Quick Facts
Patent No.
US 12,724,712
App. No.
18/625,084
Granted
Sep 1, 2026
Kind
B2
Abstract

Various embodiments include techniques for migrating points of coherence (PoCs) in a cache hierarchy. The techniques comprise receiving, at a first cache memory and from a second cache memory, a memory access request associated with a first scope group, and, in response to determining a first directory within the first cache memory includes a first entry indicating (i) a third cache memory is a child of the first cache memory in a tree associated with the first scope group, and (ii) the first cache memory is a root of the tree associated with the first scope group: performing one or more operations to acquire a PoC token from a descendant cache memory of the first cache memory in the tree associated with the first scope group, and updating the first entry to indicate that the first cache memory is a PoC of the tree associated with the first scope group.

Claims (47)

1 . A computer-implemented method for migrating a point of coherence in a cache hierarchy, the method comprising:

receiving, at a first cache memory and from a second cache memory coupled to the first cache memory, a memory access request associated with a first scope group; and

in response to determining that a first directory residing within the first cache memory includes a first entry indicating that (i) a third cache memory is a child of the first cache memory in a tree associated with the first scope group, and (ii) the first cache memory is a root of the tree associated with the first scope group:

performing one or more operations to acquire a point of coherence token from a descendant cache memory of the first cache memory in the tree associated with the first scope group, and

updating the first entry to indicate that the first cache memory is a point of coherence of the tree associated with the first scope group.

2 . The computer-implemented method of claim 1 , further comprising updating a second entry in a second directory residing within the descendant cache memory to indicate that the descendant cache memory is a branch of the tree associated with the first scope group.

3 . The computer-implemented method of claim 1 , wherein performing the one or more operations to acquire the point of coherence token comprises:

transmitting, from the first cache memory to the descendant cache memory, a request for the point of coherence token;

updating the first entry to indicate that the first cache memory is in a transient state; and

receiving the point of coherence token from the descendant cache memory,

wherein the first entry is updated from indicating that the first cache memory is in the transient state to indicating that the first cache memory is the point of coherence.

4 . The computer-implemented method of claim 1 , further comprising:

receiving, from the descendant cache memory, consistent data associated with the first scope group and the memory access request;

storing the consistent data in the first cache memory; and

responding to the memory access request with the consistent data.

5 . The computer-implemented method of claim 4 , further comprising causing a controller to defer responding to the memory access request until after the consistent data is received from the descendant cache memory.

6 . The computer-implemented method of claim 1 , wherein the first entry comprises a vector that includes a pointer to the third cache memory.

7 . The computer-implemented method of claim 1 , wherein the descendant cache memory is the third cache memory.

8 . The computer-implemented method of claim 1 , further comprising updating the first entry to indicate that the second cache memory is a child of the first cache memory in the tree associated with the first scope group.

9 . The computer-implemented method of claim 1 , wherein the first cache memory resides in a first level of a cache hierarchy and the second cache memory resides in a second level of the cache hierarchy.

10 . The computer-implemented method of claim 9 , wherein the second level of the cache hierarchy is closer than the first level of the cache hierarchy to a processing unit that issued the memory access request.

11 . One or more non-transitory computer readable media including instructions that, when executed, cause a scope tree controller to perform the steps of:

receiving, at a first cache memory and from a second cache memory coupled to the first cache memory, a memory access request associated with a first scope group; and

in response to determining that a first directory residing within the first cache memory includes a first entry indicating that (i) a third cache memory is a child of the first cache memory in a tree associated with the first scope group, and (ii) the first cache memory is a root of the tree associated with the first scope group:

performing one or more operations to acquire a point of coherence token from a descendant cache memory of the first cache memory in the tree associated with the first scope group, and

updating the first entry to indicate that the first cache memory is a point of coherence of the tree associated with the first scope group.

12 . The one or more non-transitory computer readable media of claim 11 , wherein the instructions further cause the scope tree controller to perform the step of updating a second entry in a second directory residing within the descendant cache memory to indicate that the descendant cache memory is a branch of the tree associated with the first scope group.

13 . The one or more non-transitory computer readable media of claim 12 , wherein, prior to updating the second entry, the second entry indicates that the descendant cache memory is the point of coherence of the tree associated with the first scope group.

14 . The one or more non-transitory computer readable media of claim 11 , wherein performing the one or more operations to acquire the point of coherence token comprises:

transmitting, from the first cache memory to the descendant cache memory, a request for the point of coherence token;

updating the first entry to indicate that the first cache memory is in a transient state; and

receiving the point of coherence token from the descendant cache memory,

wherein the first entry is updated from indicating that the first cache memory is in the transient state to indicating that the first cache memory is the point of coherence.

15 . The one or more non-transitory computer readable media of claim 11 , wherein the instructions further cause the scope tree controller to perform the steps of:

receiving, from the descendant cache memory, consistent data associated with the first scope group and the memory access request;

storing the consistent data in the first cache memory; and

responding to the memory access request with the consistent data.

16 . The one or more non-transitory computer readable media of claim 15 , wherein the instructions further cause the scope tree controller to perform the step of causing a controller to defer responding to the memory access request until after the consistent data is received from the descendant cache memory.

17 . The one or more non-transitory computer readable media of claim 11 , wherein the descendant cache memory is the third cache memory.

18 . The one or more non-transitory computer readable media of claim 11 , wherein the first cache memory resides in a first level of a cache hierarchy and the second cache memory resides in a second level of the cache hierarchy, and the second level of the cache hierarchy is closer than the first level of the cache hierarchy to a processing unit that issued the memory access request.

19 . The one or more non-transitory computer readable media of claim 11 , wherein the second cache memory is coupled to a processing unit that issued the memory access request.

20 . A system comprising:

a portion of a scope tree controller that resides within a first cache memory in a cache hierarchy, wherein, in operation, the portion of the scope tree controller:

receives, from a second cache memory coupled to the first cache memory, a memory access request associated with a first scope group; and

in response to determining that a first directory residing within the first cache memory includes a first entry indicating that (i) a third cache memory is a child of the first cache memory in a tree associated with the first scope group, and (ii) the first cache memory is a root of the tree associated with the first scope group:

performs one or more operations to acquire a point of coherence token from a descendant cache memory of the first cache memory in the tree associated with the first scope group, and

updates the first entry to indicate that the first cache memory is a point of coherence of the tree associated with the first group.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2024
From: OSWALD, NICOLAI ALEXANDER; BOLOTIN, EVGENY; LUSTIG, DANIEL JOSEPH; NELLANS, DAVID; TREICHLER, SEAN J.
To: NVIDIA CORPORATION
Reel/Frame 067424/0482 →
Continuity (1)
Related Publication 20250307148A1 · Oct 2, 2025
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