Granted Patent B2

US 12,517,828 · App. 18/626,212 · Granted Jan 6, 2026

Inventors: Robert Nasry Hasbun (San Jose, CA); Timothy M. Hollis (Meridian, ID); Jeffrey P. Wright (Boise, ID); Dean D. Gans (Nampa, ID)

G06F12/0806H04L5/0007H04L27/14

Abstract

Claims (38)

1 . A method, comprising:

transmitting, over a data bus by a memory device according to a first clock frequency and according to a double-data-rate (DDR) signaling scheme, a first signal that is representative of first sensed data and that is modulated according to a first modulation scheme having a first number of levels;

determining to use a second clock frequency and a second modulation scheme for transmitting a second signal representative of second sensed data, the second modulation scheme having a second number of levels; and

transmitting, over the data bus by the memory device according to the second clock frequency and according to the DDR signaling scheme, the second signal that is representative of the second sensed data and that is modulated according to the second modulation scheme.

2 . The method of claim 1 , wherein the first sensed data and the second sensed data are sensed from a dynamic random-access memory (DRAM) array of the memory device.

3 . The method of claim 1 , further comprising:

determining a signaling mode of the memory device, wherein the first signal, the second signal, or both, are transmitted based at least in part on the signaling mode.

4 . The method of claim 1 , further comprising:

detecting a change in an operating parameter, wherein the second clock frequency, the second modulation scheme, or both is based at least in part on detecting the change in the operating parameter.

5 . The method of claim 1 , wherein the first clock frequency and the first modulation scheme are associated with a first data rate.

6 . The method of claim 5 , wherein the second clock frequency and the second modulation scheme are associated with a second data rate.

7 . The method of claim 1 , wherein the first number of levels is two levels and the second number of levels is more than two levels.

8 . The method of claim 1 , wherein the second number of levels is two levels and the first number of levels is more than two levels.

9 . A memory device that operates according to a double-data-rate (DDR) signaling scheme, comprising:

a volatile memory array; and

a data bus, the memory device configured to:

transmit, over the data bus according to a first clock frequency and according to the DDR signaling scheme, a first signal that is representative of first sensed data and that is modulated according to a first modulation scheme having a first number of levels;

determine to use a second clock frequency and a second modulation scheme for transmitting a second signal representative of second sensed data, the second modulation scheme having a second number of levels; and

transmit, over the data bus according to the second clock frequency and according to the DDR signaling scheme, the second signal that is representative of the second sensed data and that is modulated according to the second modulation scheme.

10 . The memory device of claim 9 , wherein the first sensed data and the second sensed data are sensed from a dynamic random-access memory (DRAM) array of the memory device.

11 . The memory device of claim 9 , wherein the memory device is configured to:

determine a signaling mode of the memory device, wherein the first sensed data, the second sensed data, or both, are transmitted based at least in part on the signaling mode.

12 . The memory device of claim 9 , wherein the memory device is configured to:

detect a change in an operating parameter, wherein the second clock frequency, the second modulation scheme, or both is based at least in part on detecting the change in the operating parameter.

13 . The memory device of claim 9 , wherein the first clock frequency and the first modulation scheme are associated with a first data rate.

14 . The memory device of claim 13 , wherein the second clock frequency and the second modulation scheme are associated with a second data rate.

15 . The memory device of claim 9 , wherein the first number of levels is two levels and the second number of levels is more than two.

16 . The memory device of claim 9 , wherein the second number of levels is two levels and the first number of levels is more than two levels.

17 . A method, comprising:

transmitting, over a data bus by a memory device according to a double-data-rate (DDR) signaling scheme, a first signal that is representative of first sensed data and that is modulated according to a first modulation scheme having a first number of levels;

determining to use a second modulation scheme for transmitting a second signal representative of second sensed data over the data bus, the second modulation scheme having a second number of levels; and

transmitting, over the data bus by the memory device according to the DDR signaling scheme, the second signal that is representative of the second sensed data and that is modulated according to the second modulation scheme.

18 . The method of claim 17 , wherein the first signal is communicated according to a first clock frequency, and wherein the second signal is communicated according to a second clock frequency.

19 . The method of claim 18 , wherein the first clock frequency is higher than the second clock frequency.

20 . The method of claim 17 , further comprising:

transmitting, over the data bus by the memory device according to the DDR signaling scheme, a third signal that is representative of third sensed data and that is modulated according to the first modulation scheme.

21 . The method of claim 20 , further comprising:

transmitting, over the data bus by the memory device according to the DDR signaling scheme, a fourth signal that is representative of fourth sensed data and that is modulated according to the second modulation scheme.

Continuity (5)

References Cited (203)