Granted Patent B2

US 12,299,661 · App. 18/628,864 · Granted May 13, 2025

Inventors: Cory Douthat (San Francisco, CA); Jason Binder (San Francisco, CA); Matthew Maibach (San Francisco, CA); Thomas Byrne (Oakland, CA)

Assignee: Block, Inc.

G06Q20/206G06Q20/382

Abstract

Claims (30)

1. A system for controlling access to an interface device, the system comprising:

a processor that communicates with the interface device through a switch while the switch is in a first state;

the switch, wherein the switch toggles from the first state to a second state in response to detection of a suspicious behavior associated with the processor, wherein the switch electrically couples the interface device to the processor in the first state, wherein the switch electrically decouples the interface device from the processor in the second state; and

the interface device, wherein the interface device communicates with the processor through the switch to operate a user interface using the interface device while the switch is in the first state.

2. The system of claim 1 , wherein the interface device includes an output device.

3. The system of claim 1 , wherein the interface device includes an input device.

4. The system of claim 1 , wherein the interface device includes a codec.

5. The system of claim 1 , wherein the interface device includes a touchscreen.

6. The system of claim 1 , wherein the interface device includes at least one of a speaker, a headset, or a microphone.

7. The system of claim 1 , wherein the interface device includes a network communication interface that communicates over a network.

8. The system of claim 1 , further comprising:

tamper detection circuitry, wherein the suspicious behavior is associated with a tamper attempt detected using the tamper detection circuitry.

9. The system of claim 1 , wherein the suspicious behavior is associated with network activity.

10. The system of claim 1 , wherein the suspicious behavior is associated with a malfunction by the processor.

11. The system of claim 1 , wherein the suspicious behavior is associated with data to be received by the processor.

12. The system of claim 1 , wherein the suspicious behavior is associated with data to be output by the processor.

13. The system of claim 1 , wherein the processor is prevented from performing a specific type of operation while the switch is in the second state.

14. The system of claim 1 , further comprising:

a diode that prevents data flow across the switch in a first direction to restrict data flow across the switch to a second direction.

15. The system of claim 1 , further comprising:

a second processor, wherein the switch electrically couples the interface device to the second processor in the second state, wherein the switch electrically decouples the interface device from the second processor in the first state.

16. The system of claim 1 , further comprising:

a second processor that detects the suspicious behavior associated with the processor, wherein the second processor causes the switch to toggle from the first state to the second state in response to the detection of the suspicious behavior by the second processor.

17. The system of claim 1 , wherein the processor detects the suspicious behavior associated with the processor, wherein the processor causes the switch to toggle from the first state to the second state in response to the detection of the suspicious behavior by the processor.

18. A method controlling access to an interface device, the method comprising:

conveying one or more communications between a processor and the interface device through a switch to operate a user interface using the interface device while the switch is in a first state, wherein the switch electrically couples the interface device to the processor in the first state;

detecting a suspicious behavior associated with the processor, and

toggling the switch from the first state to a second state in response to the detection of the suspicious behavior associated with the processor, wherein the switch electrically decouples the interface device from the processor in the second state.

19. The method of claim 18 , wherein the interface device includes an output device.

20. The method of claim 18 , wherein the interface device includes an input device.

Assignments (1)

Continuity (4)

References Cited (228)