IP Library › Granted Patent US 12,548,634
Granted Patent B2
US 12,548,634 · App. 18/630,895 · Granted Feb 10, 2026

Peak power management connectivity check in a memory device

Inventors: Eleuterio Mannella (L'Aquila, IT); Massimo Rossini (Rome, IT)
Assignee: Micron Technology, Inc.
G11C29/38G06F1/04G06F1/26
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Quick Facts
Patent No.
US 12,548,634
App. No.
18/630,895
Granted
Feb 10, 2026
Kind
B2
Abstract

A memory device includes a plurality of memory dies, each memory die of the plurality of memory dies comprising a memory array and a power management component, operatively coupled with the memory array. The power management component sends a test value to one or more other power management components on one or more other memory dies of the plurality of memory dies and receives one or more other test values from the one or more other power management components. The power management component compares the test value and the one or more other test values to a set of expected values, and responsive to the test value and the one or more other test values matching the set of expected values, determines that signal connections between the power management component and the one or more other power management components are functional.

Claims (47)

1 . A memory device comprising:

a plurality of memory dies; and

a peak power management system, the peak power management system comprising respective peak power management components disposed on each memory die of the plurality of memory dies,

wherein the respective peak power management components are operatively coupled with each other to share clock and data signals over signal connections in a closed-loop system, wherein the clock and data signals are not accessible from off the memory device, and

wherein the respective peak power management components are configured to:

transmit and receive test information over the signal connections during a connectivity test sequence to verify physical connectivity between the peak power management components; and

determine whether the signal connections between the peak power management components are functional based on the test information exchanged during the connectivity test sequence.

2 . The memory device of claim 1 , wherein to perform the peak power management component connectivity check, a first peak power management component of the respective peak power management components is configured to perform operations comprising:

sending a first test value to one or more other peak power management components on one or more other memory dies of the plurality of memory dies during a first power management token loop; and

receiving one or more other test values from the one or more other peak power management components during the first power management token loop, wherein at least one of the one or more other test values is different than the test value, and wherein the test value and the one or more other test values are derived from a seed value according to a defined test value scheme.

3 . The memory device of claim 2 , wherein the peak power management component connectivity check is initiated in response to receipt of a first command requesting initialization of the peak power management component connectivity check on the memory device, wherein the first command comprises an indication of the seed value and the defined test value scheme.

4 . The memory device of claim 2 , wherein, according to the test value scheme, the test value comprises the seed value, and wherein alternating ones of the one or more other test values comprise an inverse of the seed value.

5 . The memory device of claim 2 , wherein, according to the test value scheme, the test value comprises the seed value, and wherein respective ones of the one or more other test values comprise an increment of the seed value.

6 . The memory device of claim 2 , wherein the test value and the one or more other test values are stored in a register associated with the first peak power management component.

7 . The memory device of claim 6 , wherein to perform the peak power management component connectivity check, the first peak power management component of the respective peak power management components is configured to perform operations further comprising:

comparing the test value and the one or more other test values to a set of expected values; and

responsive to the test value and the one or more other test values matching the set of expected values, determining that signal connections between the peak power management component and the one or more other peak power management components are functional.

8 . The memory device of claim 7 , wherein to perform the peak power management component connectivity check, the first peak power management component of the respective peak power management components is configured to perform operations further comprising:

receiving a second command requesting validation of the peak power management component connectivity check on the memory device, wherein the second command comprises an indication of the seed value and the test value scheme.

9 . The memory device of claim 8 , wherein to perform the peak power management component connectivity check, the first peak power management component of the respective peak power management components is configured to perform operations further comprising:

responsive to receiving the second command, determining the set of expected values based on the seed value and the test value scheme, wherein comparing the test value and the one or more other test values to a set of expected values comprises reading the test value and the one or more other test values from the register.

10 . The memory device of claim 9 , wherein to perform the peak power management component connectivity check, the first peak power management component of the respective peak power management components is configured to perform operations further comprising:

receiving a third command requesting results of the validation; and

responsive to receiving the third command, returning an indication of the results of the validation, the indication indicating whether the test value and the one or more other test values match the set of expected values.

11 . A memory device comprising:

a plurality of memory dies, each memory die of the plurality of memory dies comprising:

a memory array; and

a peak power management component, operatively coupled with the memory array and with each other peak power management component to share clock and data signals over signal connections in a closed-loop system, wherein the clock and data signals are not accessible from off the memory device, and wherein the peak power management component is to:

transmit and receive test information over the signal connections during a connectivity test sequence to verify physical connectivity between the peak power management components; and

determine whether the signal connections between the peak power management components are functional based on the test information exchanged during the connectivity test sequence.

12 . The memory device of claim 11 , wherein to perform the peak power management component connectivity check, the peak power management component is configured to perform operations comprising:

sending a first test value to each other peak power management component on one or more other memory dies of the plurality of memory dies during a first power management token loop; and

receiving one or more other test values from each other peak power management component during the first power management token loop, wherein at least one of the one or more other test values is different than the test value, and wherein the test value and the one or more other test values are derived from a seed value according to a defined test value scheme.

13 . The memory device of claim 12 , wherein the peak power management component connectivity check is initiated in response to receipt of a first command requesting initialization of the peak power management component connectivity check on the memory device, wherein the first command comprises an indication of the seed value and the defined test value scheme.

14 . The memory device of claim 12 , wherein, according to the test value scheme, the test value comprises the seed value, and wherein alternating ones of the one or more other test values comprise an inverse of the seed value.

15 . The memory device of claim 12 , wherein, according to the test value scheme, the test value comprises the seed value, and wherein respective ones of the one or more other test values comprise an increment of the seed value.

16 . The memory device of claim 12 , wherein the test value and the one or more other test values are stored in a register associated with the first peak power management component.

17 . The memory device of claim 16 , wherein to perform the peak power management component connectivity check, the peak power management component is configured to perform operations further comprising:

comparing the test value and the one or more other test values to a set of expected values; and

responsive to the test value and the one or more other test values matching the set of expected values, determining that signal connections between the peak power management component and the one or more other peak power management components are functional.

18 . The memory device of claim 17 , wherein to perform the peak power management component connectivity check, the peak power management component is configured to perform operations further comprising:

receiving a second command requesting validation of the peak power management component connectivity check on the memory device, wherein the second command comprises an indication of the seed value and the test value scheme.

19 . The memory device of claim 18 , wherein to perform the peak power management component connectivity check, the peak power management component is configured to perform operations further comprising:

responsive to receiving the second command, determining the set of expected values based on the seed value and the test value scheme, wherein comparing the test value and the one or more other test values to a set of expected values comprises reading the test value and the one or more other test values from the register.

20 . The memory device of claim 19 , wherein to perform the peak power management component connectivity check, the peak power management component is configured to perform operations further comprising:

receiving a third command requesting results of the validation; and

responsive to receiving the third command, returning an indication of the results of the validation, the indication indicating whether the test value and the one or more other test values match the set of expected values.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2024
From: MANNELLA, ELEUTERIO; ROSSINI, MASSIMO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 067068/0266 →
Continuity (3)
Continuation 17248728 · Feb 4, 2021
Provisional Application 63199358 · Dec 21, 2020
Related Publication 20240257892A1 · Aug 1, 2024
References Cited (23)
US 7234070B2 · James · 2007 [cited by applicant]
US 7505683B1 · Lemieux · 2009 [cited by examiner]
US 8090965B1 · Chakravarty · 2012 [cited by applicant]
US 9865360B2 · Sharon et al. · 2018 [cited by applicant]
US 10446254B1 · Zehavi et al. · 2019 [cited by applicant]
US 11133038B1 · Tang · 2021 [cited by examiner]
US 20070021848A1 · Huang · 2007 [cited by applicant]
US 20080222474A1 · Hiraide et al. · 2008 [cited by applicant]
US 20080229163A1 · Niijima et al. · 2008 [cited by applicant]
US 20120124441A1 · Teng et al. · 2012 [cited by applicant]
US 20120319717A1 · Chi · 2012 [cited by applicant]
US 20130326263A1 · Alameldeen et al. · 2013 [cited by applicant]
US 20140201252A1 · Brocker et al. · 2014 [cited by applicant]
US 20160093400A1 · Botea · 2016 [cited by applicant]
US 20160342187A1 · Ha · 2016 [cited by examiner]
US 20170185463A1 · Kim et al. · 2017 [cited by applicant]
US 20190065089A1 · Myers et al. · 2019 [cited by applicant]
US 20210248032A1 · Kang · 2021 [cited by examiner]
US 20220148663A1 · Guo · 2022 [cited by examiner]
US 20220164117A1 · Guo · 2022 [cited by examiner]
CN 107731264A · 2018 [cited by applicant]
JP 2007317229A · 2007 [cited by applicant]
Office Action for Chinese Patent Application No. CN202111565677.6, mailed Dec. 4, 2025, 11 Pages. (Best available copy). [cited by applicant]