Vertical memory devices and methods for operating the same
A method for performing an erasing operation on a memory device is provided. The memory device includes a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar, and a bit line formed above the drain cap. A first positive voltage bias is applied to the bottom select gate. A second positive voltage bias is applied to the plate line. The first positive voltage bias to the bottom select gate is reduced. A negative voltage bias is applied to the source line.
1. A method for performing an erasing operation on a memory device, wherein the memory device comprises a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar, and a bit line formed above the drain cap, the method comprising:
applying a first positive voltage bias to the bottom select gate;
applying a second positive voltage bias to the plate line;
reducing the first positive voltage bias to the bottom select gate; and
applying a negative voltage bias to the source line.
2. The method of claim 1 , wherein applying the negative voltage bias to the source line occurs after the bottom select gate reaches the reduced first positive voltage bias.
3. The method of claim 1 , further comprising increasing the second positive voltage bias to the plate line.
4. The method of claim 1 , further comprising increasing the first positive voltage bias to the bottom select gate.
5. The method of claim 1 , further comprising decreasing the second positive voltage bias to the plate line.
6. The method of claim 3 , further comprising:
during a first time period, reducing the first positive voltage bias to the bottom select gate and increasing the second positive voltage bias to the plate line.
7. The method of claim 1 , further comprising applying a negative voltage bias to the source line after the reducing the first positive voltage bias to the bottom select gate.
8. A method for performing an erasing operation on a memory device, wherein the memory device comprises a plate line, a bias gate above the plate line, a word line above the plate line, a pillar extending through the plate line, the bias gate, and the word line, a source line under the pillar, a drain cap above the pillar and a bit line formed above the drain cap, the method comprising:
applying a first positive voltage bias to the bias gate;
applying a second positive voltage bias to the plate line;
reducing the first positive voltage bias to the bias gate; and
applying a negative voltage bias to the source line.
9. The method of claim 8 , wherein applying the negative voltage bias to the source line occurs after the bias gate reaches the reduced first positive voltage bias.
10. The method of claim 8 , further comprising increasing the second positive voltage bias to the plate line.
11. The method of claim 8 , further comprising increasing the first positive voltage bias to the bias gate.
12. The method of claim 8 , further comprising decreasing the second positive voltage bias to the plate line.
13. The method of claim 10 , further comprising:
during a first time period, reducing the first positive voltage bias to the bias gate and increasing the second positive voltage bias to the plate line.
14. The method of claim 8 , further comprising applying a negative voltage bias to the source line after the reducing the first positive voltage bias to the bias gate.
15. A memory device, comprising:
a bottom select gate;
a plate line above the bottom select gate;
a word line above the plate line;
a pillar extending through the bottom select gate, the plate line, and the word line;
a source line under the pillar;
a drain cap above the pillar; and
a circuit coupled to the bottom select gate, the plate line and the source line, and configured to:
apply a first positive voltage bias to the bottom select gate;
apply a second positive voltage bias to the plate line;
reduce the first positive voltage bias to the bottom select gate; and
apply a negative voltage bias to the source line.
16. The memory device of claim 15 , wherein applying the negative voltage bias to the source line occurs after the bottom select gate reaches the reduced first positive voltage bias.
17. The memory device of claim 15 , wherein the circuit further configured to:
increase the second positive voltage bias to the plate line.
18. The memory device of claim 15 , wherein the circuit further configured to:
increase the first positive voltage bias to the bottom select gate.
19. The memory device of claim 15 , wherein the circuit further configured to:
decrease the second positive voltage bias to the plate line.
20. The memory device of claim 17 , wherein the circuit further configured to:
during a first time period, reduce the first positive voltage bias to the bottom select gate and increase the second positive voltage bias to the plate line.