IP Library › Granted Patent US 51,036

Granted Patent E1

US 51,036 · App. 18/631,750 · Granted Sep 15, 2026

Method and system for decoding

Inventors: Warren Gross (Montreal, CA); Saied Hemati (Montreal, CA); Shie Mannor (Montreal, CA); Ali Naderi (Montreal, CA); Francois Leduc-Primeau (Montreal, CA)

Assignee: Polar Technologies LLC

H03M13/1137 H03M13/1117 H03M13/1142 H03M13/1151 H03M13/3707 H03M13/6544 H03M13/6575 H03M13/6577

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Quick Facts

Patent No.: US 51,036
App. No.: 18/631,750
Granted: Sep 15, 2026
Kind: E1

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USPTO Patent Center↗ Full Patent PDF↗

Abstract

Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. They also offer performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with code length. They also offer challenges relating to decoding complexity and error floors limiting achievable bit-error rates. Accordingly encoders with reduced complexity, reduced power consumption and improved performance are disclosed with various improvements including simplifying communications linking multiple processing nodes by passing messages where pulse widths are modulated with the corresponding message magnitude, delaying a check operation in dependence upon variable node states, running the decoder multiple times with different random number generator seeds for a constant channel value set, and employing a second decoder with a randomizing component when the attempt with the first decoder fails.

Claims (187)

1 . A method comprising:

providing a decoder for decoding received digital data according to a decoding process comprising a plurality of processing nodes, wherein

at least one of:

(A) the decoder further comprises linking a common control line to a predetermined portion of the plurality of processing nodes wherein each processing node of the plurality of processing nodes comprises at least a control port coupled to the common control line for receiving a control message, and transmitting the control message on the common control line wherein the width of a pulse transmitted is modulated in dependence with a magnitude associated with the control message;

(B) the decoding process comprises estimating a probability associated with a predetermined portion of the decoding process in dependence upon the states of a predetermined subset of the plurality of processing nodes and a current belief relating to the decoding process;

(C) the decoder further comprises providing a random number generator and executing a predetermined portion of the decoding process multiple times on the same received digital data wherein each execution is performed with a different seed for the random number generator;

(D) the decoder further comprises providing a second decoder comprising a component to randomize the decoding trajectory of the second decoder wherein digital content is parsed to the second decoder upon determining that the decoder has failed to decode the received digital data, the digital content being one of the decoded result of the decoder and the received digital data;

(E) the decoder further comprises providing a counter forming a predetermined portion of the decoder and operating the counter at a first clock rate, the first clock rate being at a higher clock rate than a second clock rate relating to the rest of the decoder;

(F) the decoder further comprises providing a variable node as part of the decoder, providing a check node as cart of the decoder, providing an edge linking the variable node and the check node and providing a clock having a first clock and a second clock rate wherein the clock is coupled to the variable node and the one of the first clock rate and second clock rate for the clock is established in dependence upon a transition relating to the edge; and

(G) the decoder further comprises a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes, a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes, and the decoding process comprises passing a current belief and information relating to the state of the plurality of processing nodes to an estimator to estimate a probability, delaying a parity check determination relating to the plurality of check nodes, the delay being determined in dependence upon at least the states of the plurality of variable nodes, and performing a parity check operation relating to the plurality of check nodes, the parity check operation made in dependence upon the level of agreement of the variable nodes.

2 . The method according to claim 1 further comprising;

providing a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes;

providing a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes; and

determining a parity check relating to a predetermined subset of the plurality of check nodes in dependence upon a level of agreement between a predetermined subset of the plurality of variable nodes.

3 . The method according to claim 1 further comprising;

providing a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes;

providing a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes; and

delaying a parity check determination relating to the plurality of check nodes, the delay being determined in dependence upon at least the states of the plurality of variable nodes.

4 . A device comprising:

a decoder for decoding received digital data according to a decoding process comprising a plurality of processing nodes, the decoder comprising;

at least one of:

(A) a common control line coupled to a predetermined portion of the plurality of processing nodes, each processing node of the plurality of processing nodes comprising at least a control port coupled to the common control line for receiving a control message, and a transmitter for transmitting the control message on the common control line wherein the width of a pulse transmitted is modulated in dependence with a magnitude associated with the control message;

(B) an estimator for estimating a probability associated with a predetermined portion of the decoding process in dependence upon the states of a predetermined subset of the plurality of processing nodes and a current belief relating to the decoding process,

(C) a random number generator; and multiple executions of a predetermined portion of the decoding process multiple times on the same received digital data, each execution being performed with a different seed for the random number generator; and

(D) a second decoder comprising a component to randomize the decoding trajectory of the second decoder; wherein digital content is parsed to the second decoder upon determining that the decoder has failed to decode the received digital data, the digital content being one of the decoded result of the decoder and the received digital data.

5 . The device according to claim 4 further comprising;

a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes;

a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes; and

a parity checker for determining a parity check relating to a predetermined subset of the plurality of check nodes in dependence upon a level of agreement between a predetermined subset of the plurality of variable nodes.

6 . The device according to claim 4 further comprising;

a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes;

a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes; and

a delay circuit for delaying a parity check determination relating to the plurality of check nodes, the delay being determined in dependence upon at least the states of the plurality of variable nodes.

7 . The device according to claim 4 further comprising;

a counter forming a predetermined portion of the decoder; wherein

the counter is operated at a first clock rate, the first clock rate being at a higher clock rate than a second clock rate relating to the rest of the decoder.

8 . The device according to claim 4 further comprising;

a variable node as part of the decoder;

a check node as part of the decoder;

an edge linking the variable node and the check node;

a clock generator for providing a clock having a first clock rate and a second clock rate to the variable node, the one of the first clock rate and second clock rate for the clock being determined in dependence upon a transition relating to the edge.

9 . The device according to claim 4 wherein,

a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes;

a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes;

an estimator for generating an estimate a probability in dependence upon a current belief and information relating to the state of the plurality of processing nodes;

a parity checker for performing a parity check operation relating to the plurality of check nodes in dependence upon the level of agreement of the variable nodes.

10 . A device comprising:

a decoder for decoding received digital data according to a decoding process comprising a plurality of processing nodes, the decoder comprising;

at least one of:

(A) a counter forming a predetermined portion of the decoder, wherein the counter is operated at a first clock rate, the first clock rate being at a higher clock rate than a second clock rate relating to the rest of the decoder;

(B) a variable node as part of the decoder, a check node as part of the decoder, an edge linking the variable node and the check node, and a clock generator coupled to the variable node for providing a clock having a first clock rate and a second clock rate, the one of the first clock rate and second clock rate being determined in dependence upon a transition relating to the edge; and

(C) a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes, a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes, an estimator for generating an estimate a probability in dependence upon a current belief and information relating to the state of the plurality of processing nodes, a delay circuit for delaying a parity check determination relating to the plurality of check nodes, the delay being determined in dependence upon at least the states of the plurality of variable nodes, and a parity checker for performing a parity check operation relating to the plurality of check nodes in dependence upon the level of agreement of the variable nodes.

11 . The device according to claim 10 further comprising;

a common control line coupled to a predetermined portion of the plurality of processing nodes, each processing node of the plurality of processing nodes comprising at least a control port coupled to the common control line for receiving a control message; and

a transmitter for transmitting the control message on the common control line wherein the width of a pulse transmitted is modulated in dependence with a magnitude associated with the control message.

12 . The device according to claim 10 further comprising;

an estimator for estimating a probability associated with a predetermined portion of the decoding process in dependence upon the states of a predetermined subset of the plurality of processing nodes and a current belief relating to the decoding process.

13 . The device according to claim 10 further comprising;

a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes;

a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes; and

14 . The device according to claim 10 further comprising;

a plurality of check nodes forming a first predetermined portion of the plurality of processing nodes;

a plurality of variable nodes forming a second predetermined portion of the plurality of processing nodes; and

15 . The device according to claim 10 further comprising;

a random number generator; and

multiple executions of a predetermined portion of the decoding process multiple times on the same received digital data, each execution being performed with a different seed for the random number generator.

16 . The device according to claim 10 further comprising;

a second decoder comprising a component to randomize the decoding trajectory of the second decoder; wherein

digital content is parsed to the second decoder upon determining that the decoder has failed to decode the received digital data, the digital content being one of the decoded result of the decoder and the received digital data.

17. A method for decoding digital data, comprising:

receiving digital data;

providing a decoder for decoding received digital data according to a decoding process comprising a plurality of processing nodes, the decoding process comprising a polar decoding process and the decoder comprising a polar decoder;

generating a list of candidate codewords by decoding, using the polar decoder, the digital data according to the polar decoding process, the polar decoding process comprising estimating a probability associated with a predetermined portion of the polar decoding process in dependence upon the states of a predetermined subset of the plurality of processing nodes and a current belief relating to the polar decoding process; and

generating an output message by processing. using a second decoder, at least one candidate codeword in the list of candidate codewords.

18. The method of claim 17 , wherein processing the list of candidate codewords comprises processing each codeword in the list of candidate codewords.

19. The method of claim 17 , further comprising:

providing a plurality of check nodes forming a first portion of the plurality of processing nodes;

providing a plurality of variable nodes forming a second portion of the plurality of processing nodes; and

determining a parity check relating to a subset of the plurality of check nodes in dependence upon a level of agreement between a subset of the plurality of variable nodes.

20. The method of claim 17 , wherein the polar decoder decodes the digital data based on list decoding of at least one candidate codeword in the list of candidate codewords.

21. The method of claim 17 , further comprising providing a Low-Density Parity-Check (LDPC) decoder.

22. The method of claim 17 , wherein the plurality of processing nodes comprises a set of check nodes and a set of variable nodes.

23. The method of claim 22 , wherein the current belief is based on an output of at least one of the check nodes in the set of check nodes.

24. The method of claim 22 , wherein the number of check nodes in the set of check nodes is less than the number of variable nodes in the set of variable nodes.

25. The method of claim 22 , further comprising providing, by at least one of the set of variable nodes, the estimated probability in a signal.

26. The method of claim 22 , further comprising providing, by at least one of the set of check nodes, the estimated probability in a signal.

27. The method of claim 17 , wherein the polar decoding process further comprises:

dividing the digital data into a first set of digital data and a second set of digital data;

decoding the first set of digital data using a first subset of the plurality of processing nodes to obtain a first decoded result;

decoding the second set of digital data using a second subset of the plurality of processing nodes and a second current belief based on the first decoded result to obtain a second decoded result; and

constructing at least one candidate codeword based on the first decoded result and the second decoded result.

28. The method of claim 17 , further comprising receiving the digital data via a communication channel having data-corrupting noise present in the communication channel.

29. The method of claim 17 , further comprising:

during the generating of the list of candidate codewords, detecting an error in a candidate codeword in the list of candidate codewords; and

removing the candidate codeword having the detected error from the list of candidate codewords.

30. The method of claim 17 , wherein:

the polar decoding process further comprises following distinct decoding paths within the plurality of processing nodes; and

wherein the plurality of processing nodes comprises a set of variable nodes, a set of check nodes distinct from the set of variable nodes, and a plurality of associated edges, wherein a subset of the plurality of associated edges connects a variable node in the set of variable nodes to a check node in the set of check nodes.

31. The method of claim 30 , wherein the distinct decoding paths comprise variable nodes in the set of variable nodes, check nodes in the set of check nodes, and associated edges in the plurality of associated edges connecting a particular variable node to a particular check node.

32. The method of claim 30 , wherein a subset of the set of variable nodes comprises degree-3 variable nodes.

33. The method of claim 32 , wherein a second subset of the set of variable nodes comprises degree-1 variable nodes.

34. The method of claim 30 , wherein each check node in the set of check nodes comprises a degree-1 check node.

35. The method of claim 17 , wherein the polar decoding process further comprises obtaining a received signal vector of a first polar code.

36. The method of claim 35 , wherein the polar decoding process further comprises:

searching a codeword state space based on the received signal vector to identify a candidate codeword; and

including the identified candidate codeword in the list of candidate codewords.

37. The method of claim 17 , wherein the current belief comprises a plurality of bits determined based on a subset of the plurality of processing nodes.

38. The method of claim 17 , wherein the estimated probability is based on an exclusive or operation performed on inputs to at least one of the plurality of processing nodes.

39. The method of claim 17 , wherein at least one of the plurality of processing nodes returns the current belief without any change to the states of the predetermined subset of the plurality of processing nodes.

40. The method of claim 17 , wherein each processing node in the plurality of processing nodes comprises an internal memory.

41. The method of claim 40 , wherein the internal memory of a particular processing node in the plurality of processing nodes stores a state of the particular processing node.

42. The method of claim 40 , wherein the internal memory of a particular processing node in the plurality of processing nodes stores a current belief of the particular processing node.

43. The method of claim 17 , wherein the plurality of processing nodes comprises a set of variable nodes, the method further comprising: generating, by at least one of the variable nodes in the set of variable nodes, a signal updating the states of the predetermined subset of the plurality of processing nodes.

44. The method of claim 17 , wherein the plurality of processing nodes comprises a set of variable nodes, further comprising generating by at least one variable node in the set of variable nodes, a signal updating the current belief.

45. The method of claim 17 , wherein the plurality of processing nodes comprises a set of check nodes, and wherein the method further comprises generating by each processing node in the set of check nodes, a signal comprising a predetermined value.

46. The method of claim 17 , wherein the probability comprises a log-likelihood ratio.

47. The method of claim 17 , further comprising providing, by at least one of the plurality of processing nodes, a signal comprising the probability.

48. The method of claim 17 , further comprising decoding, by the predetermined subset of the plurality of processing nodes, a portion of the received digital data.

49. The method of claim 17 , wherein the predetermined subset of the plurality of processing nodes comprises at least one variable node.

50. The method of claim 17 , wherein the predetermined subset of the plurality of processing nodes comprises at least one check node.

51. The method of claim 17 , wherein estimating the probability associated with the predetermined portion of the polar decoding process is further in dependence upon a partial decoding of the received digital data.

52. The method of claim 17 , wherein estimating the probability associated with the predetermined portion of the polar decoding process is further in dependence upon a decoding of a portion of the received digital data.

53. The method of claim 17 , wherein the predetermined portion of the polar decoding process comprises performing a check operation calculated based on the states of a subset of the plurality of processing nodes.

54. The method of claim 17 , wherein the predetermined portion of the polar decoding process comprises performing an equality check operation calculated based on the states of a predetermined subset of the plurality of processing nodes.

55. The method of claim 17 , further comprising:

passing to a second polar decoder digital content, the digital content comprising at least a portion of the received digital data and a decoded result of the received digital data by the polar decoder, wherein the digital content is passed to the second polar decoder based on a state of the decoding of the received digital data by the polar decoder, and wherein the second polar decoder alters the trajectory of the decoding of the received digital data, and

generating by the second polar decoder, at least one candidate codeword included in the list of candidate codewords.

56. A device comprising:

a decoder for decoding received digital data according to a decoding process comprising a plurality of processing nodes, wherein the decoding process comprises a polar decoding process;

the decoder comprising an estimator for estimating a probability associated with a predetermined portion of the decoding process in dependence upon the states of a predetermined subset of the plurality of processing nodes and a current belief relating to the decoding process, the estimator comprising at least a portion of the plurality of processing nodes;

the plurality of processing nodes operable to:

receive digital data;

generate a list of candidate codewords by decoding the digital data according to the decoding process comprising estimating a probability associated with a predetermined portion of the decoding process in dependence upon the states of a predetermined subset of the plurality of processing nodes and a current belief relating to the decoding process; and

generate an output message by processing, using a second decoding process, at least one of the candidate codewords in the list of candidate codewords.

57. The device of claim 56 , wherein processing the list of candidate codewords comprises processing each of the codewords in the list of candidate codewords.

58. The device of claim 56 , wherein:

the plurality of processing nodes comprises a plurality of check nodes and a plurality of variable nodes; and

the plurality of processing nodes are operable to determine a parity check relating to a subset of the plurality of check nodes in dependence upon a level of agreement between a subset of the plurality of variable nodes.

59. The device of claim 56 , wherein the decoding process decodes the digital data based on list decoding of at least one candidate codeword.

60. The device of claim 56 , further comprising a Low-Density Parity-Check (LDPC) decoder.

61. The device of claim 56 , wherein the plurality of processing nodes comprises a set of check nodes and a set of variable nodes.

62. The device of claim 61 , wherein the current belief is determined based on an output of at least one of the check nodes in the set of check nodes.

63. The device of claim 61 , wherein the number of check nodes in the set of check nodes is less than the number of variable nodes in the set of variable nodes.

64. The device of claim 61 , wherein the estimated probability is provided in a signal provided by at least one variable node in the set of variable nodes.

65. The device of claim 61 , wherein the estimated probability is provided in a signal provided by at least one check node in the set of check nodes.

66. The device of claim 56 , wherein the decoding process further comprises:

dividing the digital data into a first set of digital data and a second set of digital data;

decoding the first set of digital data using a first subset of the plurality of processing nodes to obtain a first decoded result;

decoding the second set of digital data using a second subset of the plurality of processing nodes and a belief determined based on the first decoded result to obtain a second decoded result; and

constructing at least one candidate codeword based on the first decoded result and the second decoded result.

67. The device of claim 56 , wherein the digital data is received via a communication channel having data-corrupting noise present in the communication channel.

68. The device of claim 56 , wherein the plurality of processing nodes are further operable to:

during the generating of the list of candidate codewords, detect an error in a candidate codeword in the list of candidate codewords; and

remove the candidate codeword having the detected error from the list of candidate codewords.

69. The device of claim 56 , wherein:

the decoding process comprises following distinct decoding paths within the plurality of processing nodes; and

the plurality of processing nodes comprises a set of variable nodes, a set of check nodes distinct from the set of variable nodes, and a plurality of associated edges, wherein a subset of the plurality of associated edges connects a variable node in the set of variable nodes to a check node in the set of check nodes.

70. The device of claim 69 , wherein the distinct decoding paths comprise variable nodes in the set of variable nodes, check nodes in the set of check nodes, and associated edges in the plurality of associated edges connecting a particular variable node in the set of variable nodes to a particular check node in the set of check nodes.

71. The device of claim 69 , wherein a subset of the set of variable nodes comprises degree-3 variable nodes.

72. The device of claim 71 , wherein a second subset of the set of variable nodes comprises degree-l variable nodes.

73. The device of claim 69 , wherein each check node in the set of check nodes comprises a degree-l check node.

74. The device of claim 56 , wherein the decoding process comprises obtaining a received signal vector of a first polar code.

75. The device of claim 74 , wherein the decoding process further comprises:

searching a codeword state space based on the received signal vector to identify a candidate codeword; and

including the identified candidate codeword in the list of candidate codewords.

76. The device of claim 56 , wherein the current belief comprises a plurality of bits determined based on a subset of the plurality of processing nodes.

77. The device of claim 56 , wherein the estimated probability is determined based on an exclusive or operation performed on inputs to at least one of the processing nodes in the plurality of processing nodes.

78. The device of claim 56 , wherein at least one of the processing nodes in the plurality of processing nodes returns the current belief without any change to the states of the predetermined subset of the plurality of processing nodes.

79. The device of claim 56 , wherein each processing node in the plurality of processing nodes comprises an internal memory.

80. The device of claim 79 , wherein the internal memory of a particular processing node in the plurality of processing nodes stores a state of the particular processing node.

81. The device of claim 79 , wherein the internal memory of a particular processing node in the plurality of processing nodes stores a current belief of the particular processing node.

82. The device of claim 56 , wherein the plurality of processing nodes comprises a set of variable nodes, wherein at least one variable node in the set of variable nodes generates a signal updating the states of the predetermined subset of the plurality of processing nodes.

83. The device of claim 56 , wherein the plurality of processing nodes comprises a set of variable nodes, wherein at least one variable node in the set of variable nodes generates a signal updating the current belief.

84. The device of claim 56 , wherein the plurality of processing nodes comprises a set of check nodes, wherein each check node in the set of check nodes generates a signal having a predetermined value.

85. The device of claim 56 , wherein the probability comprises a log-likelihood ratio.

86. The device of claim 56 , wherein the probability is provided in a signal provided by at least one processing node of the plurality of processing nodes.

87. The device of claim 56 , wherein the predetermined subset of the plurality of processing nodes comprises at least one processing node that has decoded a portion of the received digital data.

88. The device of claim 56 , wherein the predetermined subset of the plurality of processing nodes comprises at least one variable node.

89. The device of claim 56 , wherein the predetermined subset of the plurality of processing nodes comprises at least one check node.

90. The device of claim 56 , wherein estimating the probability associated with the predetermined portion of the decoding process is further in dependence upon a partial decoding of the received digital data.

91. The device of claim 56 , wherein estimating the probability associated with the predetermined portion of the decoding process is further in dependence upon a decoding of a portion of the received digital data.

92. The device of claim 56 , wherein the predetermined portion of the decoding process comprises performing a check operation calculated based on the states of a predetermined subset of the plurality of processing nodes.

93. The device of claim 56 , wherein the predetermined portion of the decoding process comprises performing an equality check operation calculated based on the states of a predetermined subset of the plurality of processing nodes.

94. The device of claim 56 , further comprising a second plurality of processing nodes for decoding digital content according to the decoding process, the second plurality of processing nodes operable to alter a trajectory of the decoding of the received digital data, the digital content being passed to the second plurality of processing nodes based on a state of the decoding of the received digital data by the plurality of processing nodes, the digital content comprising at least a portion of the received digital data and a decoded result of the received digital data by the plurality of processing nodes, the second plurality of processing nodes further operable to generate at least one candidate codeword included in the list of candidate codewords.

Continuity (7)

Continuation 18222335 · Jul 14, 2023

Reissue 13216373 · Aug 24, 2011

Provisional Application 61392544 · Oct 13, 2010

Provisional Application 61385602 · Sep 23, 2010

Provisional Application 61377114 · Aug 26, 2010

Provisional Application 61376801 · Aug 25, 2010

Reissue 13216373 · Aug 24, 2011

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