Granted Patent B2

US 12,597,927 · App. 18/632,137 · Granted Apr 7, 2026

Inventor: Abhishek Jain (Noida, IN)

Assignee: STMicroelectronics International N.V.

H03K19/00338H03K3/0372H03K3/0375

Abstract

Claims (49)

1 . A device, comprising:

a main flip-flop including:

a main data input terminal;

a main data output terminal; and

a plurality of secondary flip-flops each having:

a data input terminal coupled to the main data input terminal;

a data output terminal;

an alternate data input terminal; and

an enable terminal configured to selectively enable the data input terminal or the data output terminal.

2 . The device of claim 1 , wherein the main flip-flop includes an error detection circuit having:

an input side coupled to the data output of each of the secondary flip-flops; and

an output side coupled to the alternate data input terminal of each of the secondary flip-flops.

3 . The device of claim 2 , wherein the output side of the error detection circuit outputs a respective enable signal to the enable terminal of each secondary flip-flop.

4 . The device of claim 3 , wherein respective enable signal indicates whether or not an error state has been detected for the corresponding secondary flip-flop.

5 . The device of claim 4 , wherein the plurality of secondary flip-flops includes:

a first secondary flip-flop, wherein the output side of the error detection circuit outputs a first enable signal to the enable terminal of the first secondary flip-flop;

a second secondary flip-flop, wherein the output side of the error detection circuit outputs a second enable signal to the enable terminal of the second secondary flip-flop; and

a third secondary flip-flop, wherein the output side of the error detection circuit outputs a third enable signal to the enable terminal of the third secondary flip-flop.

6 . The device of claim 2 , wherein the plurality of secondary flip-flops includes:

a first secondary flip-flop; and

a second secondary flip-flop, wherein the output side of the error detection circuit outputs an enable signal to the enable terminal of the first secondary flip-flop and to the enable terminal of the second secondary flip-flop.

7 . The device of claim 6 , wherein the enable signal indicates whether there is an error state among at one of the first and second secondary flip-flops.

8 . The device of claim 2 , wherein the alternate data input terminal of each secondary flip-flop is connected to the main output of the main flip-flop.

9 . The device of claim 2 , wherein the alternate data input terminal of each secondary flip-flop is connected to the output terminal of another of the plurality of secondary flip-flops.

10 . The device of claim 2 , wherein the main flip-flop includes a comparison circuit having:

an input side coupled to the data output terminals of two or more of the secondary flip-flops; and

an output side configured to provide a data value to the main output terminal.

11 . The device of claim 10 , wherein the main flip-flop includes an inverter coupled between the output side of the comparison circuit and the main output terminal.

12 . A method, comprising:

receiving, at a main input terminal of a main flip-flop, a data value, the main flip-flop including a plurality of secondary flip-flops;

providing the data value from the main input terminal to a respective data input terminal of each of a plurality of secondary flip-flops, each secondary flip-flop including an alternate data input terminal, an enable terminal, and an output terminal;

receiving, at the alternate data input terminal of each secondary flip-flop, a respective alternate input data value;

outputting, from the output terminal of each of the secondary flip-flops, a respective output data value to an error detection circuit;

outputting, from the error detection circuit, a respective enable signal to the enable terminal of each secondary flip-flop; and

for each secondary flip-flop, selectively passing to the output terminal of the secondary flip-flop either the data value or the alternate input data value based on the enable signal.

13 . The method of claim 12 , wherein each respective enable signal indicates whether or not an error state has been detected for the corresponding secondary flip-flop.

14 . The method of claim 12 , comprising generating a main output data value of the flip-flop based on the output data value of two or more of the secondary flip-flops.

15 . The method of claim 14 , comprising receiving, at the alternate data input terminal of each secondary flip-flop, the main output data value as the alternate input data value.

16 . The method of claim 14 , comprising receiving, at the alternate data input terminal of each secondary flip-flop, the output data value of another of the secondary flip-flops.

17 . The method of claim 12 , generating the main output data value with a comparison circuit based on the output data value of two or more of the secondary flip-flops.

18 . A method, comprising:

providing an input data value of a main flip-flop to a data input terminal of each of a plurality of secondary flip-flops of the main flip-flop;

receiving, at an alternate data input terminal of each of the secondary flip-flops, a respective alternate input data value;

detecting, for each secondary flip-flop with an error detection circuit of the main flip-flop, whether an error state is present at the secondary flip-flop; and

selectively outputting, for each secondary flip-flop, the alternate input data value as an output data value based on whether or not the error state is present.

19 . The method of claim 18 , comprising generating a main output value of the main flip-flop based on the output data value of two or more of the secondary flip-flops.

20 . The method of claim 18 , comprising:

changing the main output value only if the two or more output data values are all the same; and

retaining a previous value of the main output value if the two or more output data values are not all the same.

Assignments (1)

Continuity (2)

References Cited (60)