Multicomponent photonically bridged assembly
A package comprises a first die and a bridging element. The first die includes a compute element and/or memory element, a first region, a first portion of a photonic transceiver, and a first die interconnect region. The first region intersects a center of the first die. The first portion of a photonic transceiver includes and AMS block with a driver and transimpedance amplifier, coupled with the first die interconnect region. The bridging element includes a modulator and photodetector, connected with a bridging interconnect region. An optical interface, photonically linked with the first photonic transceiver, routes packets from an external device optical interface to the compute and/or memory element.
1. A package comprising:
a first die, comprising:
a first compute element and/or a first memory element;
a first region, wherein the first region intersects a center of the first die;
a first portion of a first photonic transceiver comprising a first AMS block that includes a driver (DRV) and a transimpedance amplifier (TIA); and
a first die interconnect region electrically coupled with the first portion of the first photonic transceiver; and
a first bridging element, comprising:
a second portion of the first photonic transceiver, including a modulator (MOD 1 ) and a photodetector (PD 1 );
a first bridging interconnect region for electrically coupling the first portion of the first photonic transceiver with the second portion of the first photonic transceiver; and
an optical interface (OI), photonically coupled via a first photonic path with the second portion of the first photonic transceiver.
2. The package of claim 1 , wherein the optical interface OI is configured to photonically route a packet from an external device optical interface via the OI and the first photonic transceiver to the first compute element and/or the first memory element.
3. The package of claim 1 , wherein the first portion and the second portion of the first photonic transceiver are coupled via an electrical interconnect less than about two millimeters (2 mm) in length.
4. The package of claim 1 , wherein the first AMS block is adjacent to an edge of the first region and proximate to the first compute element and/or the first memory element.
5. The package of claim 1 , wherein the first region includes at least one of a memory, a cache memory, other shared memory, a network on-chip crossbar, a switch, a routing mechanism, or a memory controller.
6. The package of claim 1 , wherein the first region is located centrally in the first die to even out latencies between the first compute element and the first region.
7. The package of claim 1 , further comprising:
a second bridging element photonically bridging two compute elements on the first die.
8. The package of claim 1 , further comprising:
a second die, comprising:
a second compute element and/or second memory element;
a second region, wherein the second region intersects a center of the second die;
a first portion of a second photonic transceiver comprising a second AMS block that includes a driver (DRV) and a transimpedance amplifier (TIA); and
a second die interconnect region electrically coupled with the first portion of the second photonic transceiver;
wherein the first bridging element further comprises:
a second portion of the second photonic transceiver, including a modulator (MOD 1 ) and a photodetector (PD 1 ); and
a second bridging interconnect region for electrically coupling the first portion of the second photonic transceiver with the second portion of the second photonic transceiver.
9. The package of claim 8 , wherein the first die and the second die each include multiple compute elements.