IP Library Granted Patent US 12,277,499
Granted Patent B2
US 12,277,499 · App. 18/636,640 · Granted Apr 15, 2025

Vector computation unit in a neural network processor

Inventors: Gregory Michael Thorson (Waunakee, WI); Christopher Aaron Clark (Madison, WI); Dan Luu (Madison, WI)
Assignee: Google LLC
G06N3/08G06F5/08G06F7/544G06N3/063G06N5/04
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Quick Facts
Patent No.
US 12,277,499
App. No.
18/636,640
Granted
Apr 15, 2025
Kind
B2
Abstract

A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.

Claims (54)

1. A vector computation unit for performing neural network computations comprising:

normalization circuitry configured to:

receive a vector of activation values;

receive one or more control signals specifying a normalization function; and

apply the normalization function to the activation values to generate respective normalized values for each activation value.

2. The vector computation unit of claim 1 , wherein the one or more control signals are provided by a sequencer.

3. The vector computation unit of claim 1 , further comprising activation circuitry configured to:

receive a vector of accumulated values;

receive one or more control signal specifying an activation function; and

apply the activation function to the accumulated values to generate the vector of activation values.

4. The vector computation unit of claim 3 , wherein the accumulated values correspond to products of a matrix multiplication between a layer of the neural network and a parameter matrix for the layer.

5. The vector computation unit of claim 1 , further comprising pooling circuitry configured to:

receive the normalized values;

receive one or more control signals specifying a pooling function; and

apply the pooling function to the normalized values to generate a pooled value.

6. The vector computation unit of claim 5 , wherein the pooled value comprises at least one of a maximum, a minimum, or an average of the activation values, or a maximum, a minimum, or an average of a subset of the activate values.

7. The vector computation unit of claim 5 , wherein the pooling circuitry comprises multiple parallel pooling circuitries, each pool circuitry configured to receive a subset of the activation values to generate a respective pooled value.

8. The vector computation unit of claim 1 , wherein applying the normalization function to the activation values comprises:

determining a sum of the activation values;

determining a multiplication factor based on the sum of the activation values; and

multiplying the activation values by the multiplication factor to generate the normalized values.

9. The vector computation unit of claim 1 , further comprising a plurality of registers and a plurality of memory units configured to store the activation values.

10. A method for performing neural network computations comprising:

receiving, by normalization circuitry of a vector computation unit, a vector of activation values;

receiving, by the normalization circuitry, one or more control signals specifying a normalization function; and

applying, by the normalization circuitry, the normalization function to the activation values to generate respective normalized values for each activation value.

11. The method of claim 10 , wherein the one or more control signals are provided by a sequencer.

12. The method of claim 10 , further comprising:

receiving, by activation circuitry of the vector computation unit, a vector of accumulated values;

receiving, by the activation circuitry, one or more control signal specifying an activation function; and

applying, by the activation circuitry, the activation function to the accumulated values to generate the vector of activation values.

13. The method of claim 12 , wherein the accumulated values correspond to products of a matrix multiplication between a layer of the neural network and a parameter matrix for the layer.

14. The method of claim 10 , further comprising:

receiving, by pooling circuitry of the vector computation unit, the normalized values;

receiving, by the pooling circuitry, one or more control signals specifying a pooling function; and

applying, by the pooling circuitry, the pooling function to the normalized values to generate a pooled value.

15. The method of claim 14 , wherein the pooled value comprises at least one of a maximum, a minimum, or an average of the activation values, or a maximum, a minimum, or an average of a subset of the activate values.

16. The method of claim 14 , wherein the pooling circuitry comprises multiple parallel pooling circuitries, each pool circuitry configured to receive a subset of the activation values to generate a respective pooled value.

17. The method of claim 10 , wherein applying the normalization function to the activation values comprises:

determining a sum of the activation values;

determining a multiplication factor based on the sum of the activation values; and

multiplying the activation values by the multiplication factor to generate the normalized values.

18. A non-transitory computer readable medium for storing instructions executable by a processor to perform neural network computations, the instructions comprising:

receiving a vector of activation values;

receiving one or more control signals specifying a normalization function; and

applying the normalization function to the activation values to generate respective normalized values for each activation value.

19. The non-transitory computer readable medium of claim 18 , wherein the instructions further comprise:

receiving a vector of accumulated values;

receiving one or more control signal specifying an activation function; and

applying the activation function to the accumulated values to generate the vector of activation values.

20. The non-transitory computer readable medium of claim 18 , wherein the instructions further comprise:

receiving the normalized values;

receiving one or more control signals specifying a pooling function; and

applying the pooling function to the normalized values to generate a pooled value.

Assignments (2)
CHANGE OF NAME Recorded Apr 17, 2024
From: GOOGLE INC.
To: GOOGLE LLC
Reel/Frame 067133/0504 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2024
From: THORSON, GREGORY MICHAEL; CLARK, CHRISTOPHER AARON; LUU, DAN
To: GOOGLE INC.
Reel/Frame 067120/0548 →
Continuity (5)
Continuation 18176640 · Mar 1, 2023
Continuation 16245406 · Jan 11, 2019
Continuation 14845117 · Sep 3, 2015
Provisional Application 62165022 · May 21, 2015
Related Publication 20240273368A1 · Aug 15, 2024
References Cited (152)
US 3761876A · Flaherty · 1973 [cited by applicant]
US 3777132A · Bennett, Jr. · 1973 [cited by applicant]
US 4717807A · Parks et al. · 1988 [cited by applicant]
US 4839836A · Fonsalas · 1989 [cited by applicant]
US 5005149A · Elleaume et al. · 1991 [cited by applicant]
US 5014235A · Morton · 1991 [cited by applicant]
US 5136717A · Morley et al. · 1992 [cited by applicant]
US 5138695A · Means · 1992 [cited by applicant]
US 5146543A · Vassiliadis et al. · 1992 [cited by applicant]
US 5337395A · Vassiliadis et al. · 1994 [cited by applicant]
US 5471627A · Means et al. · 1995 [cited by applicant]
US 5519811A · Yoneda · 1996 [cited by applicant]
US 5544336A · Kato · 1996 [cited by applicant]
US 5799134A · Chiueh et al. · 1998 [cited by applicant]
US 5809341A · Nimishakvi et al. · 1998 [cited by applicant]
US 5812993A · Ginosar et al. · 1998 [cited by applicant]
US 6038337A · Lawrence · 2000 [cited by applicant]
US 6184753B1 · Ishimi et al. · 2001 [cited by applicant]
US 7136710B1 · Hoffberg · 2006 [cited by applicant]
US 8184696B1 · Chirila-Rus · 2012 [cited by applicant]
US 8468109B2 · Moussa et al. · 2013 [cited by applicant]
US 8924455B1 · Barman et al. · 2014 [cited by applicant]
US 9886948B1 · Garimella et al. · 2018 [cited by applicant]
US 10074051B2 · Thorson et al. · 2018 [cited by applicant]
US 10102481B2 · Kim et al. · 2018 [cited by applicant]
US 20020038294A1 · Matsugu · 2002 [cited by applicant]
US 20030076992A1 · Banish et al. · 2003 [cited by applicant]
US 20050044053A1 · Moreno · 2005 [cited by applicant]
US 20070022063A1 · Lightowler · 2007 [cited by applicant]
US 20070086655A1 · Simard et al. · 2007 [cited by applicant]
US 20080319933A1 · Moussa · 2008 [cited by applicant]
US 20100312735A1 · Knoblauch · 2010 [cited by applicant]
US 20110029471A1 · Chakradhar et al. · 2011 [cited by applicant]
US 20130246745A1 · Hatano et al. · 2013 [cited by applicant]
US 20140129601A1 · Olsen · 2014 [cited by applicant]
US 20140142929A1 · Seide et al. · 2014 [cited by applicant]
US 20140180989A1 · Krizhevsky et al. · 2014 [cited by applicant]
US 20140280989A1 · Borkowski et al. · 2014 [cited by applicant]
US 20140288928A1 · Penn et al. · 2014 [cited by applicant]
US 20140337262A1 · Kato et al. · 2014 [cited by applicant]
US 20140344203A1 · Ahn · 2014 [cited by applicant]
US 20150117760A1 · Wang et al. · 2015 [cited by applicant]
US 20160267111A1 · Shoaib · 2016 [cited by applicant]
US 20160275341A1 · Li et al. · 2016 [cited by applicant]
US 20180082107A1 · Li et al. · 2018 [cited by applicant]
CN 102665049A · 2012 [cited by applicant]
CN 104035751A · 2014 [cited by applicant]
CN 104145281A · 2014 [cited by applicant]
CN 104485715A · 2015 [cited by applicant]
EP 0422348A2 · 1991 [cited by applicant]
EP 2259214A1 · 2010 [cited by applicant]
EP 3064130A1 · 2016 [cited by applicant]
GB 2558271A · 2018 [cited by applicant]
JP S63206828A · 1988 [cited by applicant]
JP H02170263A · 1990 [cited by applicant]
JP H03253966A · 1991 [cited by applicant]
JP 2002519720A · 2002 [cited by applicant]
JP 2002304288A · 2002 [cited by applicant]
JP 2015036939A · 2015 [cited by applicant]
JP 2015095215A · 2015 [cited by applicant]
KR 1019910003516 · 1991 [cited by applicant]
KR 20130090147A · 2013 [cited by applicant]
KR 20150016089A · 2015 [cited by applicant]
KR 20150032738A · 2015 [cited by applicant]
TW 200627103A · 2006 [cited by applicant]
TW 201232429A · 2012 [cited by applicant]
TW 201331855A · 2013 [cited by applicant]
Farabet et al, “CNP: An fpga-based processor for convolutional networks”, International Conference on Field Programmable Logic and Applications, 2009, 6 pages. [cited by applicant]
KR Notice of Allowance in Korean Application No. 10-2017-7028169, dated Mar. 20, 2020, 4 pages (with English translation). [cited by applicant]
IN Office Action in Indian Application No. 201747034436, dated May 4, 2020, 6 pages (with English translation). [cited by applicant]
JP Office Action in Japanese Application No. 2019-142868, dated Jun. 30, 2020, 9 pages (with English translation). [cited by applicant]
Tanomoto et al, “Convolutional Neural Network Processing on a Memory Intensive Array Accelerator” Library Naist, 2015, 51 pages. [cited by applicant]
Kusuda, “Development and evaluation of instruction generation method for distributed memory array accelerator” Library Naist, 2014, 48 pages. [cited by applicant]
Ishii et al, “Analysis of General Object Recognition Technique Using Convolutional Neural Network” IPSJ SIG Technical Report, 2014, 14 pages. [cited by applicant]
CN Office Action in Chinese Application No. 201680019810.9, dated Oct. 21, 2020, 7 pages (with English translation). [cited by applicant]
Examination Report for United Kingdom Patent Application No. 1715525.0 dated Apr. 22, 2021. 8 pages. [cited by applicant]
Office Action for United Kingdom Patent Application No. 1715525.0 dated Dec. 10, 2021. 6 pages. [cited by applicant]
Korekado et al. A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture. 2003. Springer. 8 pages. [cited by applicant]
Brosch et al. Computing with a Canonical Neural Circuits Model with Pool Normalization and Modulating Feedback. 2014. Neural Computation, vol. 26, pp. 2735-2789. [cited by applicant]
Notice of Allowance for Korean Patent Application No. 10-2020-7018024 dated Dec. 23, 2021. 2 pages. [cited by applicant]
Riesenhuber et al. Hierarchical Models of Object Recognition in Cortex. 1999. Nature Neuroscience, vol. 2, No. 11, New York, pp. 1019-1025. Retrieved from the Internet: <https://doi.org/10.1038/14819>. [cited by applicant]
Serre et al. Object Recognition with Features Inspired by Visual Cortex. 2005. 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition, vol. 2, Picastaway, pp. 994-1000. Retrieved from the Inter… [cited by applicant]
Mutch et al. Multiclass Object Recognition with Sparse, Localized Features. 2006. 2006 IEEE Computer Society Conference on Computer Vision and Pattern Recognition, vol. 3, Picastaway, pp. 11-18. Retrieved from the Inter… [cited by applicant]
Siagian et al. Rapid Biologically-Inspired Scene Classification Using Features Shared with Visual Attention. 2007. IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 29, No. 2, Picastaway, pp. 300-312.… [cited by applicant]
Ranzato et al. Unsupervised Learning of Invariant Feature Hierarchies with Applications to Object Recognition. 2007. 2007 IEEE Computer Society Conference on Computer Vision and Pattern Recognition, vol. 4, Picastaway, … [cited by applicant]
Scherer et al. Evaluation of Pooling Operations in Convolutional Architectures for Object Recognition. 2010. Lecture Notes in Computer Science, vol. 6354, Berlin, pp. 92-101. Retrieved from the Internet: <https://doi.or… [cited by applicant]
Combined Search and Examination Report for United Kingdom Patent Applicaton No. 2200642.3 dated Feb. 14, 2022. 10 pages. [cited by applicant]
Office Action for Korean Patent Application No. 10-2022-7009700 dated Jun. 23, 2022. 4 pages. [cited by applicant]
Analysis of general object recognition methods using a Convolutional Neural Network. Research Report Computer Vision and Image Media (CVIM), and an image medium (CVIM). vol. 2014—CVIM—192 No. 14,1-8, [online], May 8, 20… [cited by applicant]
Office Action for Japanese Patent Application No. 2021-148010 dated Nov. 15, 2022. 5 pages. [cited by applicant]
Notice of Allowance for Korean Patent Application No. 10-2022-7009700 dated Dec. 27, 2022. 3 pages. [cited by applicant]
Lecun et al. Efficient BackProp. Neural Networks: Tricks of the Trade. Springer, Berlin, Heidelberg, 2012. pp. 9-48. [cited by applicant]
Office Action for German Patent Application No. 112016002296.4 dated Jan. 9, 2023. 10 pages. [cited by applicant]
Office Action for Japanese Patent Application No. 2021-148010 dated Jun. 6, 2023. 2 pages. [cited by applicant]
Extended European Search Report for European Patent Application No. 23197533.5 dated Oct. 13, 2023. 12 pages. [cited by applicant]
Office Action for Korean Patent Application No. 10-2023-7010250 dated Nov. 15, 2023. 5 pages. [cited by applicant]
Hearing Notice for Indian Patent Application No. 201747034436 dated Dec. 8, 2023. 3 pages,. [cited by applicant]
First Office Action for Chinese Patent Application No. 202110718015.1 dated Mar. 8, 2024. 11 pages. [cited by applicant]
Notice of Allowance for Korean Patent Application No. 10-2023-7010250 dated Aug. 23, 2024. 3 pages. [cited by applicant]
O'Shea et al. An Introduction to Convolutional Neural Networks. arXiv preprint arXiv:1511.08458. Dec. 2, 2015. 11 pages. [cited by applicant]
International Search Report and Written Opinion in International Application No. PCT/US2016/029968, dated Sep. 1, 2016, 14 pages. [cited by applicant]
International Search Report and Written Opinion in International Application No. PCT/US2016/029294, dated Sep. 1, 2016, 13 pages. [cited by applicant]
International Search Report and Written Opinion in International Application No. PCT/US2016/029986, dated Sep. 1, 2016, 13 pages. [cited by applicant]
International Search Report and Written Opinion in International Application No. PCT/US2016/029965, dated Sep. 1, 2016, 13 pages. [cited by applicant]
Krizhevsky et al., “ImageNet classification with deep convolutional neural networks,” The 26th annual conference on Neural Information Processing Systems (NIPS'25), Dec. 2012, pp. 1-9, XP55113686. [cited by applicant]
Kung, “VLSI Array Processors,” IEEE ASSP Magazine, IEEE, vol. 2, No. 3, Jul. 1, 1985, pp. 4-22, XP011370547. [cited by applicant]
International Preliminary Report on Patentability issued in International Application No. PCT/US2016/029986, dated Nov. 30, 2017, 7 pages. [cited by applicant]
Dielman, Sander, Kyle W. Willett, and Joni Dambre. “Rotation-invariant convolutional neural networks for galaxy morphology prediction,” Monthly notices of the royal astronomical society, 450.2, 2015, pp. 1441-1459. [cited by applicant]
Kim et al. “Efficient Hardware Architecture for Sparse Coding,” IEEE Transactions on Signal Processing 62.16, Aug. 15, 2014, 14 pages. [cited by applicant]
Lee, Yim-Kul, and William T. Rhodes. “Nonlinear image processing by a rotating kernel transformation,” Optics letters 15.23, 1990, pp. 1383-1385. [cited by applicant]
Lo, Shih-Chung B., et al. “Artificial convolutional neural network for medical image pattern recognition,” Neural networks 8.7, 1995, pp. 1201-1214. [cited by applicant]
Merolla et al. “A digital Neurosynaptic Core Using Embedded Crossbar Memory with 45pJ per Spike in 45nm,” IEEE CICC, Sep. 19, 2011, 4 pages. [cited by applicant]
Beamer et al., “Ivy Bridge Server Graph Processing Bottlenecks,” The First International Workshop Computer Architecture for Machine Learning, Jun. 2015, 56pages. [cited by applicant]
Bo et al., “String Kernel Testing Acceleration Using Micron's Automata Processor,” The First International Workshop Computer Architecture for Machine Learning, Jun. 2015, 21 pages. [cited by applicant]
Chen and Li, “Hardware Acceleration for Neuromorphic Computing—An Evolving View,” The First International Workshop Computer Architecture for Machine Learning, Jun. 2015, 38 pages. [cited by applicant]
Chillet et al., “A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures,” Proceedings of International Joint Conference on Neural Networks, Aug. 2007, pp. 102-107. [cited by applicant]
Farabet et al., “Hardware Accelerated Convolutional Neural Networks for Synthetic Vision Systems,” Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, May-Jun. 2010, pp. 257-260. [cited by applicant]
Ginosar, “Accelerators for Machine Learning of Big Data,” The First International Workshop Computer Architecture for Machine Learning, Jun. 2015, 13 pages. [cited by applicant]
Gokhale, “Enabling Machines to Understand our World,” The First International Workshop Computer Architecture for Machine Learning, Jun. 2015, 18 pages. [cited by applicant]
Indiveri, “Neuromorphic circuits for building autonomous cognitive systems,” The First International Workshop Computer Architecture for Machine Learning, Jun. 2015, 37 pages. [cited by applicant]
Kane, “An instruction systolic array architecture for multiple neural network types,” Loughborough University, Doctoral Thesis, Sep. 1998, 315 pages. [cited by applicant]
Khan and Ling, “Systolic architectures for artificial neural nets,” Neural Networks, 1991. 1991 IEEE International Joint Conference on, vol. 1, Nov. 1991, pp. 620-627. [cited by applicant]
Lee and Song, “Implementation of the Super-Systolic Array for Convolution,” Design Automation Conference, 2003. Proceedings of the ASP-DAC 2003. Asia and South Pacific, Jan. 2003, pp. 491-494. [cited by applicant]
Lehmann et al., “A generic systolic array building block for neural networks with on-chip learning,” Neural Networks, IEEE Transactions on, 4(3):400-407, May 1993. [cited by applicant]
Lipasti et al., Mimicking the Self-Organizing Properties of the Visual Cortex, The First International Workshop Computer Architecture for Machine Learning, Jun. 2015, 23 pages. [cited by applicant]
Mahapatra et al., “Mapping of Neural Network Models onto Systolic Arrays,” Journal of Parallel and Distributed Computing 60, 677-689, Jan. 2000. [cited by applicant]
Ovtcharov et al., “Accelerating Deep Convolutional Neural Networks Using Specialized Hardware in the Datacenter,” The First International Workshop Computer Architecture for Machine Learning, Jun. 2015, 33 pages. [cited by applicant]
Pearce, “You Have No (Predictive) Power Here, SPEC!” The First International Workshop Computer Architecture for Machine Learning, Jun. 2015, 15 pages. [cited by applicant]
Rojas, “Hardware for Neural Networks,” Neural Networks, Springer-Verlag, Berlin, 1996, pp. 451-478. [cited by applicant]
Shaaban, “Systolic Architectures,” PowerPoint Presentation, Mar. 2003, 9 pages. [cited by applicant]
Shapri and Rahman, “Performance Analysis of Two-Dimensional Systolic Array Matrix Multiplication with Orthogonal Interconnections,” International Journal on New Computer Architectures and Their Applications (IJNCAA) 1(3… [cited by applicant]
Smith, “Biologically Plausible Spiking Neural Networks,” The First International Workshop Computer Architecture for Machine Learning, Jun. 2015, 77 pages. [cited by applicant]
Sudha et al., “Systolic array realization of a neural network-based face recognition system,” Industrial Electronics and Applications, 2008, ICIEA 2008, 3rd IEEE Conference on, pp. 1864-1869, Jun. 2009. [cited by applicant]
Wong et al., “A New Scalable Systolic Array Processor Architecture for Discrete Convolution,” College of Engineering at the University of Kentucky, Master Thesis, 2003, 175 pages. [cited by applicant]
Carlo et al., “An Area-Efficient 2-D Convolution Implementation on FPGA for Space Applications,” IEEE Computer Society, Dec. 11, 2011, pp. 1-7. [cited by applicant]
Cornu et al., “Design, Implementation, and Test of a Multi-Model Systolic Neural-Network Accelerator,” Scientific Programming—Parallel Computing Projects of the Swiss Priority Programme, vol. 5, No. 1, Jan. 1, 1996, pp.… [cited by applicant]
Dawwd, “The multi 2D systolic design and implementation of Convolutional Neural Networks,” 2013 IEEE 20.sup.th International Conference on Electronics, Circuits, and Systems (ICECS), IEEE, Dec. 8, 2013, pp. 221-224, XP0… [cited by applicant]
Graf et al., “A Massively Parallel Digital Learning Processor,” Proceedings of the 22.sup.nd annual conference on Neural Information Processing Systems (NIPS), Dec. 2008, 8 pages, XP055016863. [cited by applicant]
Hecht et al., “An advanced programmable 2D-convolution chip for, real time image processing,” Signal Image and Video Processing, Jun. 1991; [Proceedings of the International Symposium on Circuits and Systems], vol. SYMP… [cited by applicant]
International Search Report and Written Opinion in International Application No. PCT/US2016/030515, dated Aug. 25, 2016, 19 pages. [cited by applicant]
International Search Report and Written Opinion in International Application No. PCT/US2016/030536, dated Aug. 31, 2016, 17 pages. [cited by applicant]
Kim et al., “A Large-Scale Architecture for Restricted Boltzmann Machines,” Field-Programmable Custom Computing Machines (FCCM), 2010 18th IEEE Annual International Symposium on, IEEE, May 2, 2010, pp. 201-208, XP031681… [cited by applicant]
Kung et al., “Two-level pipelined systolic array for multidimensional convolution,” Image and Vision Computing, Elsevier, vol. 1, No. 1, Feb. 2, 1983, pp. 30-36, XP024237511. [cited by applicant]
Patil et al., “Hardware Architecture for Large Parallel Array of Random Feature Extractors applied to Image Recognition,” Dec. 24, 2015, arXiv:1512.07783v1, 18 pages, XP055296121. [cited by applicant]
Wu et al., “Flip-Rotate-Pooling Convolution and Split Dropout on Convolution Neural Networks for Image Classification,” Jul. 31, 2015, arXiv:1507.08754v1, pp. 1-9, XP055296122. [cited by applicant]
Office Action in Taiwanese Application No. 105115859, dated Nov. 16, 2016, 10 pages. [cited by applicant]
Mping et al (“A High Performance Digital Neural Processor Design by Network on Chip Architecture” IEEE 2011). [cited by applicant]
AHM Shapri and N.A.Z Rahman. “Performance Ananlysis of Two-Dimensional Systolic Array Matrix Multiplication with Orthogonal Interconnections.” International Journal on NewComputer Architectures and Their Applications, 1… [cited by applicant]
EP Office Action in European U.S. Appl. No. 16/724,517, dated Feb. 14, 2020, 4 pages. [cited by applicant]
CN Office Action in Chinese Application No. 201680019810, dated Mar. 16, 2020, 15 pages (with English translation). [cited by applicant]
Bernardi et al. A programmable BIST for DRAM testing and diagnosis. Jan. 20, 2011. 2010 IEEE International Test Conference. pp. 1-10. [cited by applicant]
Notice of Grant for Chinese Patent Application No. 202110718015.1 dated Sep. 23, 2024. 5 pages. [cited by applicant]