Robust and accurate overlay target design for CMP
A metrology system may receive a plurality of candidate design variations of a target layout of an overlay target. A metrology system may determine one or more process-induced target defects for the plurality of candidate design variations when fabricated with a known fabrication process. A metrology system may determine one or more process-induced overlay errors associated with the one or more process-induced target defects for the plurality of candidate design variations when measured with a known metrology recipe. A metrology system may select a final design variation from the plurality of candidate design variations that provides a smallest aggregate overlay error based on the one or more process-induced overlay errors.
1 . A system comprising:
a controller including one or more processors configured to execute program instructions stored on a memory device, wherein the program instructions cause the one or more processors to:
receive a plurality of candidate design variations of a target layout of an overlay target;
determine one or more process-induced target defects for the plurality of candidate design variations when fabricated with a known fabrication process;
determine one or more process-induced overlay errors associated with the one or more process-induced target defects for the plurality of candidate design variations when measured with a known metrology recipe; and
select a final design variation from the plurality of candidate design variations that provides a smallest aggregate overlay error based on the one or more process-induced overlay errors.
2 . The system of claim 1 , wherein the program instructions cause the one or more processors to direct one or more process tools to fabricate the overlay target with the final design variation on a sample.
3 . The system of claim 2 , wherein the program instructions cause the one or more processors to determine an overlay measurement for the overlay target based on measurement data from one or more metrology tools generated with the known metrology recipe.
4 . The system of claim 1 , wherein the one or more process-induced overlay errors comprise:
a class of avoidable process-induced overlay errors associated with a class of avoidable process-induced target defects, wherein the class of avoidable process-induced target defects is a subset of the one or more process-induced target defects;
wherein selecting the final design variation from the plurality of candidate design variations comprises selecting the final design variation without the class of avoidable process-induced target defects.
5 . The system of claim 4 , wherein the target layout includes features distributed with a coarse pitch, wherein a first subset of the plurality of candidate design variations includes an oxide in spaces between the features, wherein a second subset of the plurality of candidate design variations includes a metal in the spaces between the features, wherein the class of avoidable process-induced target defects includes target asymmetries associated with the metal in the spaces between the features, wherein selecting the final design variation from the plurality of candidate design variations comprises selecting the final design variation from the first subset of the plurality of candidate design variations.
6 . The system of claim 1 , wherein the one or more process-induced overlay errors comprise:
a class of unavoidable process-induced overlay errors associated with a class of unavoidable process-induced target defects, wherein the class of unavoidable process-induced target defects is a subset of the one or more process-induced target defects.
7 . The system of claim 6 , wherein a value of an aggregate overlay error associated with the class of unavoidable process-induced overlay errors scales with a design parameter of the target layout, wherein selecting the final design variation from the plurality of candidate design variations comprises selecting the final design variation with a value of the design parameter than provides the smallest aggregate overlay error.
8 . The system of claim 7 , wherein the design parameter comprises:
a pitch of features in the target layout.
9 . The system of claim 7 , wherein the one or more process-induced overlay errors comprise:
an additional class of unavoidable process-induced overlay errors associated with an additional class of unavoidable process-induced target defects, wherein the class of unavoidable process-induced target defects is an additional subset of the one or more process-induced target defects, wherein the value of the aggregate overlay error associated with the additional class of unavoidable process-induced overlay errors is invariant to additional design parameters of the target layout, wherein selecting the final design variation from the plurality of candidate design variations comprises deprioritizing the additional class of unavoidable process-induced target defects.
10 . The system of claim 1 , wherein at least one of the one or more process-induced target defects comprises:
a target feature asymmetry induced by a polishing process.
11 . The system of claim 1 , wherein determining the one or more process-induced overlay errors associated with the one or more process-induced target defects for the plurality of candidate design variations when measured with the known metrology recipe comprises:
simulating the one or more process-induced overlay errors associated with the one or more process-induced target defects for the plurality of candidate design variations when measured with the known metrology recipe.
12 . The system of claim 1 , wherein determining the one or more process-induced overlay errors associated with the one or more process-induced target defects for the plurality of candidate design variations when measured with the known metrology recipe comprises:
fabricating the plurality of candidate design variations on one or more test samples;
generating one or more test measurements of the plurality of candidate design variations using the known metrology recipe; and
determining the one or more process-induced overlay errors associated with the one or more process-induced target defects for the plurality of candidate design variations when measured with the known metrology recipe based on one or more test measurements.
13 . The system of claim 1 , wherein the program instructions cause the one or more processors to provide one or more overlay correctables based on one or more overlay measurements.
14 . A method for designing an overlay target comprising:
identifying a plurality of candidate design variations of a target layout of the overlay target;
determining one or more process-induced target defects for the plurality of candidate design variations when fabricated with a known fabrication process;
determining one or more process-induced overlay errors associated with the one or more process-induced target defects for the plurality of candidate design variations when measured with a known metrology recipe; and
selecting a final design variation from the plurality of candidate design variations that provides a smallest aggregate overlay error based on the one or more process-induced overlay errors.
15 . The method of claim 14 , further comprising fabricating the overlay target with the final design variation on a sample.
16 . The method of claim 15 , further comprising determining an overlay measurement for the overlay target with the known metrology recipe.
17 . The method of claim 14 , wherein the one or more process-induced overlay errors comprise:
a class of avoidable process-induced overlay errors associated with a class of avoidable process-induced target defects, wherein the class of avoidable process-induced target defects is a subset of the one or more process-induced target defects;
wherein selecting the final design variation from the plurality of candidate design variations comprises selecting the final design variation without the class of avoidable process-induced target defects.
18 . The method of claim 17 , wherein the target layout includes features distributed with a coarse pitch, wherein a first subset of the plurality of candidate design variations includes an oxide in spaces between the features, wherein a second subset of the plurality of candidate design variations includes a metal in the spaces between the features, wherein the class of avoidable process-induced target defects includes target asymmetries associated with the metal in the spaces between the features, wherein selecting the final design variation from the plurality of candidate design variations comprises selecting the final design variation from the first subset of the plurality of candidate design variations.
19 . The method of claim 14 , wherein the one or more process-induced overlay errors comprise:
a class of unavoidable process-induced overlay errors associated with a class of unavoidable process-induced target defects, wherein the class of unavoidable process-induced target defects is a subset of the one or more process-induced target defects.
20 . The method of claim 19 , wherein a value of an aggregate overlay error associated with a class of unavoidable process-induced overlay errors scales with a design parameter of the target layout, wherein selecting the final design variation from the plurality of candidate design variations comprises selecting the final design variation with a value of the design parameter than provides the smallest aggregate overlay error.
21 . The method of claim 20 , wherein the design parameter comprises:
a pitch of features in the target layout.
22 . The method of claim 20 , wherein the one or more process-induced overlay errors comprise:
an additional class of unavoidable process-induced overlay errors associated with an additional class of unavoidable process-induced target defects, wherein the class of unavoidable process-induced target defects is an additional subset of the one or more process-induced target defects, wherein the value of the aggregate overlay error associated with the additional class of unavoidable process-induced overlay errors is invariant to additional design parameters of the target layout, wherein selecting the final design variation from the plurality of candidate design variations comprises deprioritizing the additional class of unavoidable process-induced target defects.
23 . The method of claim 14 , wherein at least one of the one or more process-induced target defects comprises:
a target feature asymmetry induced by a polishing process.
24 . The method of claim 14 , wherein determining the one or more process-induced overlay errors associated with the one or more process-induced target defects for the plurality of candidate design variations when measured with the known metrology recipe comprises:
simulating the one or more process-induced overlay errors associated with the one or more process-induced target defects for the plurality of candidate design variations when measured with the known metrology recipe based.
25 . The method of claim 14 , wherein determining the one or more process-induced overlay errors associated with the one or more process-induced target defects for the plurality of candidate design variations when measured with the known metrology recipe comprises:
fabricating the plurality of candidate design variations on one or more test samples;
generating one or more test measurements of the plurality of candidate design variations using the known metrology recipe; and
determining the one or more process-induced overlay errors associated with the one or more process-induced target defects for the plurality of candidate design variations when measured with the known metrology recipe based on one or more test measurements.
26 . The method of claim 14 , further comprising providing overlay correctables based on a value of an overlay measurement to a lithography system.
27 . A system comprising:
one or more process tools configured to fabricate an overlay target on a sample using a known fabrication process;
a controller including one or more processors configured to execute program instructions stored on a memory device, wherein the program instructions cause the one or more processors to:
receive a plurality of candidate design variations of a target layout of the overlay target;
determine one or more process-induced target defects for the plurality of candidate design variations when fabricated with a known fabrication process;
determine one or more process-induced overlay errors associated with the one or more process-induced target defects for the plurality of candidate design variations when measured with a known metrology recipe;
select a final design variation from the plurality of candidate design variations that provides a smallest aggregate overlay error based on the one or more process-induced overlay errors; and
direct the one or more process tools to fabricate the overlay target with the final design variation on the sample.
28 . The system of claim 27 , wherein the program instructions cause the one or more processors to determine an overlay measurement for the overlay target based on measurement data from one or more metrology tools generated with the known metrology recipe.
29 . The system of claim 27 , wherein the program instructions cause the one or more processors to provide one or more overlay correctables based on one or more overlay measurements.