Error polarity detection for timing skew calibration
An electronic circuit comprises multiple analog-to-digital converters (ADCs), clock circuitry, and calibration circuitry. The clock circuitry is configured to provide clock signals to the multiple ADCs to advance the multiple ADCs through time-interleaved analog-to-digital (A/D) conversions. The calibration circuitry is configured to determine a magnitude of timing skew error between any two of the clock signals; apply a dither sequence to a first clock signal of the any two clock signals, wherein the first clock signal is applied to a first ADC; determine a polarity of the timing skew error by determining a polarity of gain experienced by the dither sequence from the time-interleaved A/D conversions.
1 . An electronic circuit comprising:
multiple analog-to-digital converters (ADCs);
clock circuitry configured to provide clock signals to the multiple ADCs to advance the multiple ADCs through time-interleaved analog-to-digital (A/D) conversions; and
calibration circuitry configured to:
determine a magnitude of timing skew error between any two of the clock signals;
apply a dither sequence to a first clock signal of any two clock signals, wherein the first clock signal is applied to a first ADC of the multiple ADCs and the dither sequence changes the timing skew error between the first clock signal and the other clock signal; and
determine a polarity of the timing skew error by determining a polarity of gain experienced by the dither sequence from the time-interleaved A/D conversions.
2 . The electronic circuit of claim 1 , wherein the calibration circuitry is configured to adjust a phase relation of the first clock signal and a second clock signal of the two clock signals according to the determined magnitude and polarity of the timing skew error.
3 . The electronic circuit of claim 1 , wherein the calibration circuitry is configured to:
determine a first measure of similarity of an A/D conversion by the first ADC to a preceding A/D conversion by another ADC;
determine a second measure of similarity of the A/D conversion of the first ADC to a following A/D conversion by the other ADC;
compute a difference between the first measure of similarity and the second measure of similarity as the magnitude of the timing skew error; and
adjust the phase of the first clock signal relative to a phase of another clock signal to minimize the difference between the first measure of similarity and the second measure of similarity.
4 . The electronic circuit of claim 3 , wherein the calibration circuitry is configured to:
determine multiple first products of A/D conversions of the first ADC and A/D conversions of the other ADC preceding the A/D conversions of the first ADC;
determine multiple second products of the A/D conversions of the first ADC and A/D conversions of the other ADC following the A/D conversions of the first ADC; and
average the multiple first products to determine the first measure of similarity and average the multiple second products to determine the second measure of similarity.
5 . The electronic circuit of claim 1 , wherein the calibration circuitry is configured to apply the dither sequence to the calibration circuitry to change a phase of the first clock signal according to the dither sequence.
6 . The electronic circuit of claim 5 , wherein the calibration circuitry is configured to extract the gain experienced by the dither sequence by correlating a difference between pairs of A/D conversions to the dither sequence.
7 . The electronic circuit of claim 5 , wherein the calibration circuitry is configured to:
determine a first product of an A/D conversion of the first ADC at a first sample time and an A/D conversion of the other ADC at a sample time previous to the first sample time;
determining a second product of an A/D conversion of the first ADC at a first sample time and the A/D conversion of the other ADC at a sample time following the first sample time; and
determine the polarity of the gain experienced by the dither sequence by correlating a value of the dither sequence to a difference of the first product and the second product.
8 . The electronic circuit of claim 1 , wherein the calibration circuitry is configured to adjust a phase of the first clock signal by the determined magnitude of timing skew error relative to a phase of another clock signal according to the determined polarity of the gain experienced by the dither sequence.
9 . The electronic circuit of claim 1 , wherein the multiple ADCs produce time-interleaved A/D conversions of an input analog signal having signal components in multiple Nyquist zones.
10 . A method of processing an analog signal, the method comprising:
time-interleaving analog-to-digital (A/D) conversions of the analog signal using multiple analog-to-digital converters (ADCs) according to multiple clock signals applied to the multiple ADCs;
determining a magnitude of a timing skew error between any two of the multiple clock signals;
applying a dither sequence to phase of a first clock signal of the two clock signals, wherein the first clock signal is applied to a first ADC of the multiple ADCs and the dither sequence changes the timing skew error between the first clock signal and the other clock signal; and
determining a polarity of the timing skew error by determining a polarity of gain experienced by the dither sequence by the time-interleaved A/D conversions.
11 . The method of claim 10 , including adjusting a phase of the first clock signal relative to a phase of a second clock signal of the two clock signals according to the determined magnitude and polarity of the timing skew error.
12 . The method of claim 10 ,
wherein the determining the magnitude of the timing skew error includes:
determining a first measure of similarity of a time-interleaved A/D conversion of the first ADC to a previous time-interleaved A/D conversion of another ADC;
determining a second measure of similarity of the time-interleaved A/D conversion of the first ADC to a following time-interleaved A/D conversion of the other ADC; and
computing a difference between the first measure of similarity and the second measure of similarity; and
adjusting a phase of the first clock signal relative to a phase of another clock signal to minimize the difference between the first measure of similarity and the second measure of similarity.
13 . The method of claim 12 ,
wherein the determining the first measure of similarity includes:
determining multiple first products of A/D conversions of the first ADC and A/D conversions of the other ADC preceding the A/D conversions of the first ADC; and
averaging the multiple first products to determine the first measure of similarity;
wherein the determining the second measure of similarity includes:
determining multiple second products of the A/D conversions of the first ADC and A/D conversions of the other ADC following the A/D conversions of the first ADC; and
averaging the multiple second products to determine the second measure of similarity.
14 . The method of claim 10 , wherein the time-interleaving of A/D conversions of the analog signal includes time-interleaving of A/D conversions of an input analog signal having signal components in multiple Nyquist zones.
15 . The method of claim 10 , wherein the applying the dither sequence to the first clock signal includes changing the phase of the first clock signal according to the dither sequence.
16 . The method of claim 15 , wherein the determining the polarity of the gain experienced by the dither sequence includes correlating the dither sequence with differences between adjacent pairs of interleaved A/D conversions.
17 . The method of claim 15 , wherein the determining the polarity of the gain experienced by the dither sequence includes:
determining a first product of an A/D conversion of the first ADC at a first sample time and an A/D conversion of the other ADC at a sample time previous to the first sample time;
determining a second product of an A/D conversion of the first ADC at a first sample time and the A/D conversion of the other ADC at a sample time following the first sample time; and
correlating a value of the dither sequence at the previous sample time to a difference of the first product and the second product.
18 . The method of claim 10 , including adjusting a phase of the first clock signal by the determined magnitude of timing skew error relative to a phase of another clock signal according to the determined polarity of the gain experienced by the dither sequence.
19 . A time-interleaved analog-to-digital converter (ADC) circuit, the ADC circuit comprising:
a first sub-ADC;
a second sub-ADC;
clock circuitry configured to provide a first clock signal to the first sub-ADC and a second clock signal to a second sub-ADC to advance the first and second sub-ADCs through time-interleaved analog-to-digital (A/D) conversions; and
calibration circuitry configured to:
apply a specified dither sequence to a clock phase of the second clock signal, wherein the dither sequence changes a timing skew error between the first clock signal and the second clock signal;
extract a gain experienced by the dither sequence from the time interleaved A/D conversions; and
adjust a phase relation of the first clock signal and the second clock signal according to a polarity of the extracted gain according to a polarity of the extracted gain.
20 . The ADC circuit of claim 19 , wherein the calibration circuitry is configured to:
determine a first measure of similarity of an A/D conversion by the second sub-ADC to a preceding A/D conversion by the first sub-ADC;
determine a second measure of similarity of the A/D conversion of the second sub-ADC to a following A/D conversion by the first sub-ADC;
compute a difference between the first measure of similarity and the second measure of similarity; and
adjust the phase of the second clock signal according to the polarity of the extracted gain to minimize the difference between the first measure of similarity and the second measure of similarity.