Fast PWM dimming apparatus and control method
An apparatus includes an on timer configured to determine an on time of a high-side switch of a step-down power converter, an offset current control stage configured to convert a voltage difference between a compensation signal and a predetermined reference into a current difference, a current comparison stage configured to amplify a sensed current signal, and a PWM comparator having inputs coupled to two outputs of the current comparison stage and two outputs of the offset current control stage, wherein during a load transient from a first load level to a second load level and in a first turn-on pulse of the high-side switch, the on timer is disabled so that a current flowing through the step-down power converter reaches the second load level within the first turn-on pulse of the high-side switch.
1 . An apparatus comprising:
an on timer configured to determine an on time of a high-side switch of a step-down power converter;
an offset current control stage configured to convert a voltage difference between a compensation signal and a predetermined reference into a current difference;
a current comparison stage configured to amplify a sensed current signal; and
a PWM comparator having inputs coupled to two outputs of the current comparison stage and two outputs of the offset current control stage, wherein during a load transient from a first load level to a second load level and in a first turn-on pulse of the high-side switch, the on timer is disabled so that a current flowing through the step-down power converter reaches the second load level within the first turn-on pulse of the high-side switch, and wherein during the load transient from the first load level to the second load level and in the first turn-on pulse of the high-side switch, the two outputs of the offset current control stage are disconnected from the two inputs of the PWM comparator so that the current flowing through the step-down power converter reaches the second load level within the first turn-on pulse of the high-side switch.
2 . The apparatus of claim 1 , wherein:
the step-down power converter is controlled by a constant on time control scheme during steady operation.
3 . The apparatus of claim 1 , wherein:
the first turn-on pulse of the high-side switch is triggered at a beginning of the load transient, and wherein the load transient occurs in response to a PWM dimming signal.
4 . The apparatus of claim 1 , wherein the step-down power converter comprises:
the high-side switch and a low-side switch connected in series between an input voltage bus and ground;
an inductor and a current sense resistor connected in series between a common node of the high-side switch and the low-side switch, and an output terminal of the step-down power converter; and
an output capacitor connected between the output terminal of the step-down power converter and ground.
5 . The apparatus of claim 4 , wherein the current comparison stage comprises:
a first amplifier having a non-inverting input connected to a common node of the inductor and the current sense resistor through a first resistor, and an inverting input connected to the output terminal of the step-down power converter through a second resistor;
an adjustable current source connected to the non-inverting input of the first amplifier;
a second amplifier having a non-inverting input connected to a first output of the first amplifier, and an inverting input connected to a second output of the first amplifier;
a third resistor connected between a first output of the second amplifier and an inverting input of the PWM comparator; and
a fourth resistor connected between a second output of the second amplifier and a non-inverting input of the PWM comparator.
6 . The apparatus of claim 5 , wherein:
a current flowing through the adjustable current source is proportional to the second load level.
7 . The apparatus of claim 5 , wherein the offset current control stage comprises:
a third amplifier having a non-inverting input connected to the inverting input of the second amplifier, and an inverting input connected to the non-inverting input of the second amplifier;
a compensation capacitor connected between an output of the third amplifier and ground, and wherein the third amplifier is configured to generate the compensation signal across the compensation capacitor;
a fourth amplifier having a non-inverting input configured to receive the compensation signal, and an inverting input configured to receive a predetermined reference; and
a first auxiliary switch and a second auxiliary switch coupled between outputs the fourth amplifier and the inputs of the PWM comparator.
8 . The apparatus of claim 7 , wherein:
during steady operation, both the first auxiliary switch and the second auxiliary switch are configured to be turned on so that the offset current control stage is connected to the PWM comparator; and
during the load transient from the first load level to the second load level and in the first turn-on pulse of the high-side switch, both the first auxiliary switch and the second auxiliary switch are configured to be turned off so that the offset current control stage is disconnected from the PWM comparator.
9 . The apparatus of claim 1 , further comprising:
an enable circuit configured to receive a PWM dimming signal and generate a control signal to:
enable the on timer and configure the offset current control stage to be connected to the PWM comparator during steady operation; and
disable the on timer and configure the offset current control stage to be disconnected from the PWM comparator during the load transient from the first load level to the second load level and in the first turn-on pulse of the high-side switch.
10 . The apparatus of claim 9 , wherein the enable circuit comprises a first AND gate, a second AND gate, a first inverter, a second inverter, a latch and an NOR gate, and wherein:
an input of the first inverter is configured to receive an output signal of the PWM comparator;
a first input of the first AND gate is configured to receive a gate drive enable signal;
a second input of the first AND gate is configured to receive an output signal of the first inverter;
a first input of the second AND gate is configured to receive a PWM dimming signal;
a second input of the second AND gate is configured to receive a power converter enable signal;
a data input of the latch is connected to a bias voltage bus;
a clock input of the latch is connected to an output of the first AND gate;
a clear and reset input of the latch is connected to an output of the second AND gate;
a first input of the NOR gate is connected to an output of the latch;
a second input of the NOR gate is configured to receive a signal configured to determine a pulse width of the first turn-on pulse of the high-side switch; and
an input of the second inverter is connected to an output of the NOR gate, and wherein:
the enable circuit is configured to generate an enable signal in response to a falling edge of the output signal of the PWM comparator, and wherein in response to the enable signal, the two outputs of the offset current control stage are connected to the two inputs of the PWM comparator; and
in response to the PWM dimming signal, the enable circuit is configured to generate a disable signal, and wherein in response to the disable signal, the two outputs of the offset current control stage are disconnected from the two inputs of the PWM comparator.
11 . A system comprising:
a high-side switch and a low-side switch connected in series between an input voltage bus and ground;
an inductor and a current sense resistor connected in series between a common node of the high-side switch and the low-side switch, and an output terminal of the step-down power converter;
an output capacitor connected between the output terminal of the step-down power converter and ground; and
a controller comprising:
an on timer configured to determine an on time of the high-side switch of a step-down power converter;
an offset current control stage configured to convert a voltage difference between a compensation signal and a predetermined reference into a current difference;
a current comparison stage configured to amplify a sensed current signal; and
a PWM comparator having inputs coupled to two outputs of the current comparison stage and two outputs of the offset current control stage, wherein during a load transient from a first load level to a second load level and in a first turn-on pulse of the high-side switch, the on timer is disabled so that a current flowing through the step-down power converter reaches the second load level within the first turn-on pulse of the high-side switch, and wherein during the load transient from the first load level to the second load level and in the first turn-on pulse of the high-side switch, the two outputs of the offset current control stage are disconnected from the two inputs of the PWM comparator so that the current flowing through the step-down power converter reaches the second load level within the first turn-on pulse of the high-side switch.
12 . The system of claim 11 , wherein:
the current comparison stage comprises:
a first amplifier having a non-inverting input connected to a common node of the inductor and the current sense resistor through a first resistor, and an inverting input connected to the output terminal of the step-down power converter through a second resistor;
an adjustable current source connected to the non-inverting input of the first amplifier, and wherein a current flowing through the adjustable current source is proportional to the second load level;
a second amplifier having a non-inverting input connected to a first output of the first amplifier, and an inverting input connected to a second output of the first amplifier;
a third resistor connected between a first output of the second amplifier and an inverting input of the PWM comparator; and
a fourth resistor connected between a second output of the second amplifier and a non-inverting input of the PWM comparator; and
the offset current control stage comprises:
a third amplifier having a non-inverting input connected to the inverting input of the second amplifier, and an inverting input connected to the non-inverting input of the second amplifier;
a compensation capacitor connected between an output of the third amplifier and ground, and wherein the third amplifier is configured to generate the compensation signal across the compensation capacitor;
a fourth amplifier having a non-inverting input configured to receive the compensation signal, and an inverting input configured to receive a predetermined reference; and
a first auxiliary switch and a second auxiliary switch coupled between outputs the fourth amplifier and inputs of the PWM comparator.