Buck-boost converter and hybrid control method
An apparatus includes a buck converter portion of a buck-boost converter configured to operate under a constant on-time control scheme, wherein an on-time of a high-side switch of the buck converter portion is determined by a buck on-time timer, and a boost converter portion of the buck-boost converter configured to operate under a constant off-time control scheme, wherein an off-time of a low-side switch of the boost converter portion is determined by a boost off-time timer.
1. An apparatus comprising:
an on-time timer configured to determine a turn-off edge of a first gate drive signal based on comparing a first ramp signal with a first threshold voltage proportional to an output voltage of a power converter, wherein the on-time timer is configured to determine an on-time period of a high-side switch of a buck portion of a buck-boost converter;
an off-time timer configured to determine a turn-off edge of a second gate drive signal based on comparing a second ramp signal with a second threshold voltage proportional to an input voltage of the power converter, wherein the off-time timer is configured to determine an off-time period of a low-side switch of a boost portion of the buck-boost converter; and
a current mode control device having a first output for determining a turn-on edge of the first gate drive signal and a second output for determining a turn-on edge of the second gate drive signal.
2. The apparatus of claim 1 , wherein:
the power converter is the buck-boost converter comprising:
a first high-side switch and a first low-side switch connected in series between two input terminals of the buck-boost converter, wherein the first high-side switch is the high-side switch of the buck portion;
a second high-side switch and a second low-side switch connected in series between two output terminals of the buck-boost converter, wherein the second low-side switch is the low-side switch of the boost portion; and
an inductor is connected between a common node of the first high-side switch and the first low-side switch, and a common node of the second high-side switch and the second low-side switch.
3. The apparatus of claim 2 , wherein:
the first gate drive signal is applied to the first high-side switch of the buck-boost converter through a buck control logic unit; and
the second gate drive signal is applied to the second high-side switch of the buck-boost converter through a boost control logic unit.
4. The apparatus of claim 1 , wherein:
the first ramp is generated by a first ramp generator including a first current source having a current level proportional to the input voltage of the power converter.
5. The apparatus of claim 4 , wherein:
the first ramp generator comprises the first current source, a first ramp generation switch and a first ramp generation capacitor, and wherein:
the first current source and the first ramp generation switch are connected in series; and
the first ramp generation capacitor and the first ramp generation switch are connected in parallel.
6. The apparatus of claim 5 , further comprising:
a first OR gate and an inverter, wherein:
a first input of the first OR gate is connected to an output of the inverter;
an input of the inverter is configured to receive the first gate drive signal;
a second input of the first OR gate is configured to receive a first feedback loop signal, the first feedback loop signal being configured to determine an off-time of the first gate drive signal; and
an output of the first OR gate is connected to a control terminal of the first ramp generation switch.
7. The apparatus of claim 1 , wherein:
the second ramp is generated by a second ramp generator including a second current source having a current level proportional to the output voltage of the power converter.
8. The apparatus of claim 7 , wherein:
the second ramp generator comprises the second current source, a second ramp generation switch and a second ramp generation capacitor, and wherein:
the second current source and the second ramp generation switch are connected in series; and
the second ramp generation capacitor and the second ramp generation switch are connected in parallel.
9. The apparatus of claim 8 , further comprising:
a second OR gate, wherein:
a first input of the second OR gate is configured to receive the second gate drive signal;
a second input of the second OR gate is configured to receive a second feedback loop signal, the second feedback loop signal being configured to determine an off-time of the second gate drive signal; and
an output of the second OR gate is connected to a control terminal of the second ramp generation switch.
10. The apparatus of claim 1 , further comprising:
a first comparator having an inverting input configured to receive the first threshold voltage, a non-inverting input configured to receive the first ramp signal and an output configured to determine the turn-off edge of the first gate drive signal.
11. The apparatus of claim 1 , further comprising:
a second comparator having an inverting input configured to receive the second threshold voltage, a non-inverting input configured to receive the second ramp signal and an output configured to determine the turn-off edge of the second gate drive signal.
12. A controller comprising:
an on-time timer configured to determine a turn-off edge of a first gate drive signal based on comparing a first ramp signal with a first threshold voltage proportional to an output voltage of a power converter, wherein the turn-off edge of the first gate drive signal determines an on-time period of a high-side switch of a buck portion of a buck-boost converter;
an off-time timer configured to determine a turn-off edge of a second gate drive signal based on comparing a second ramp signal with a second threshold voltage proportional to an input voltage of the power converter, wherein the turn-off edge of the second gate drive signal determines an off-time period of a low-side switch of a boost portion of the buck-boost converter; and
a current mode control device having a first output for determining a turn-on edge of the first gate drive signal and a second output for determining a turn-on edge of the second gate drive signal.
13. The controller of claim 12 , wherein:
the power converter is the buck-boost converter comprising:
a first high-side switch and a first low-side switch connected in series between two input terminals of the buck-boost converter, wherein the first high-side switch is the high-side switch of the buck portion;
a second high-side switch and a second low-side switch connected in series between two output terminals of the buck-boost converter, wherein the second low-side switch is the low-side switch of the boost portion; and
an inductor is connected between a common node of the first high-side switch and the first low-side switch, and a common node of the second high-side switch and the second low-side switch;
the first gate drive signal is applied to the first high-side switch of the buck-boost converter through a buck control logic unit; and
the second gate drive signal is applied to the second high-side switch of the buck-boost converter through a boost control logic unit.
14. The controller of claim 12 , further comprising:
the first ramp is generated by a first ramp generator including a first current source having a current level proportional to the input voltage of the power converter; and
the second ramp is generated by a second ramp generator including a second current source having a current level proportional to the output voltage of the power converter.
15. The controller of claim 12 , wherein:
the current mode control device comprises a comparator having a first input configured to receive an output voltage of an error amplifier and a second input configured to receive a signal proportional to a current flowing through an inductor of the power converter.
16. The controller of claim 15 , wherein:
the first output of the current mode control device is an output of an inverter having an input connected to an output of the comparator; and
the second output of the current mode control device is the output of the comparator.
17. A system comprising:
a buck-boost converter comprising:
a first high-side switch and a first low-side switch connected in series between two input terminals of the buck-boost converter;
a second high-side switch and a second low-side switch connected in series between two output terminals of the buck-boost converter; and
an inductor is connected between a common node of the first high-side switch and the first low-side switch, and a common node of the second high-side switch and the second low-side switch; and
a controller configured to control the buck-boost converter, the controller comprising:
an on-time timer configured to determine a turn-off edge of a first gate drive signal based on comparing a first ramp signal with a first threshold voltage, wherein the first threshold voltage is proportional to an output voltage of a power converter, wherein the turn-off edge of the first gate drive signal determines an on-time period of the first high-side switch;
an off-time timer configured to determine a turn-off edge of a second gate drive signal based on comparing a second ramp signal with a second threshold voltage, wherein the second threshold voltage is proportional to an input voltage of the power converter, wherein the turn-off edge of the second gate drive signal determines an off-time period of the second low-side switch; and
a current mode control device having a first output for determining a turn-on edge of the first gate drive signal and a second output for determining a turn-on edge of the second gate drive signal.
18. The system of claim 17 , wherein:
the first gate drive signal is applied to the first high-side switch of the buck-boost converter through a buck control logic unit; and
the second gate drive signal is applied to the second high-side switch of the buck-boost converter through a boost control logic unit.
19. The system of claim 17 , wherein:
the current mode control device comprises a comparator having a first input configured to receive an output voltage of an error amplifier and a second input configured to receive a signal proportional to a current flowing through the inductor of the buck-boost converter.
20. The system of claim 19 , wherein:
the error amplifier has a first input connected to a predetermined reference and a second input configured to detect an output voltage of the buck-boost converter.