CLOCK DATA RECOVERY CIRCUIT

1 . An isolator circuit, comprising:

a modulator circuit including an output;

an isolation capacitor including:

a first terminal coupled to the output of the modulation circuit; and

a second terminal;

a demodulator circuit including:

an input coupled to the second terminal of the isolation capacitor; and

an output terminal;

a clock data recovery circuit including:

a deglitch filter circuit coupled to the output terminal of the demodulator circuit, and configured to remove pulses having less than a particular duration from a data signal to produce a deglitched data signal; and

a timer circuit coupled to the deglitch filter circuit, and configured to:

compare a duration of a pulse of the deglitched data signal to a threshold duration; and

identify the pulse of the deglitched data signal as representing a logic one based on the duration of the pulse exceeding the threshold duration.

2 . The isolator circuit of claim 1 , wherein:

the timer circuit includes a flip-flop configured to store the logic one represented by the pulse at an end of the threshold duration; and

the timer circuit is configured to identify the pulse as representing a logic zero based on the duration of the pulse not exceeding the threshold duration.

3 . The isolator circuit of claim 2 , wherein:

the clock data recovery circuit includes a delayed pulse circuit configured to generate, responsive to a leading edge of the pulse, a reset pulse; and

the timer circuit is configured to apply the reset pulse to reset the flip-flop.

4 . The isolator circuit of claim 3 , wherein the delayed pulse circuit includes:

a delay circuit configured to delay the pulse produce a delayed pulse; and

a pulse generation circuit configured to generate the reset pulse at a leading edge of the delayed pulse.

5 . The isolator circuit of claim 1 , wherein the timer circuit includes:

an oscillator circuit configured to generate, responsive to the pulse, a clock signal having a period of the threshold duration.