Semiconductor dice for inductor-based switching power converters and associated integrated circuits and systems
A semiconductor die for an inductor-based switching power converter includes a semiconductor layer stack, a first enhancement mode, N-channel metal oxide semiconductor field effect transistor (first NMOS FET) formed in the semiconductor layer stack, a second enhancement mode, N-channel metal oxide semiconductor field effect transistor (second NMOS FET) formed in the semiconductor layer stack, first driver circuitry formed in the semiconductor layer stack, second driver circuitry formed in the semiconductor layer stack, and bootstrap capacitance. The first driver circuitry is configured to drive the first gate from a bootstrap power rail in response to a first control signal, and the second driver circuitry is configured to drive the second gate in response to a second control signal. The bootstrap capacitance includes one or more bootstrap trench capacitors formed in the semiconductor layer stack, and each bootstrap capacitor is electrically coupled between the bootstrap power rail and the switching node.
1 . A semiconductor die for an inductor-based switching power converter, the semiconductor die comprising:
a semiconductor layer stack comprising:
a P-type substrate (PSUB) and a deep N-type well (DNW) formed over the PSUB in a first direction, and
an N-type well (NWL) formed over the DNW in the first direction such that the DNW is disposed between the PSUB and the NWL in the first direction;
a first enhancement mode, N-channel metal oxide semiconductor field effect transistor (first NMOS FET) formed in the semiconductor layer stack, the first NMOS FET including a first drain, a first source, and a first gate, the first drain being electrically coupled to a first power node, and the first source being electrically coupled to a switching node;
a second enhancement mode, N-channel metal oxide semiconductor field effect transistor (second NMOS FET) formed in the semiconductor layer stack, the second NMOS FET including a second drain, a second source, and a second gate, the second drain being electrically coupled to the switching node, and the second source being electrically coupled to a second power node;
first driver circuitry formed in the semiconductor layer stack and configured to drive the first gate from a bootstrap power rail in response to a first control signal;
second driver circuitry formed in the semiconductor layer stack and configured to drive the second gate in response to a second control signal; and
bootstrap capacitance including one or more bootstrap trench capacitors formed in the semiconductor layer stack, each bootstrap trench capacitor being electrically coupled between the bootstrap power rail and the switching node, and each bootstrap trench capacitor extends into each of the DNW and the NWL in the first direction,
wherein the DNW is electrically coupled to the bootstrap power rail and the PSUB is electrically coupled to the second power node.
2 . The semiconductor die of claim 1 , wherein a respective bottom plate terminal of each of the one or more bootstrap trench capacitors is electrically coupled to the bootstrap power rail.
3 . The semiconductor die of claim 1 , wherein a respective top plate terminal of each of the one or more bootstrap trench capacitors is electrically coupled to the switching node.
4 . The semiconductor die of claim 1 , wherein:
each bootstrap trench capacitor is formed in a respective trench in the semiconductor layer stack;
each bootstrap trench capacitor includes a respective dielectric layer lining its respective trench in the semiconductor layer stack; and
each bootstrap trench capacitor includes respective conductive material filling its respective trench in the semiconductor layer stack.
5 . The semiconductor die of claim 1 , further comprising bootstrap control circuitry formed in the semiconductor layer stack and configured to control charging of the bootstrap capacitance.
6 . The semiconductor die of claim 1 , wherein the semiconductor layer stack is formed according to a complementary metal oxide semiconductor (CMOS) fabrication process.
7 . An integrated circuit for an inductor-based switching power converter, the integrated circuit comprising:
an integrated circuit package including a first power terminal, a switching terminal, and a second power terminal; and
a semiconductor die housed in the integrated circuit package, the semiconductor die including:
a semiconductor layer stack comprising:
a P-type substrate (PSUB) and a deep N-type well (DNW) formed over the PSUB in a first direction, and
an N-type well (NWL) formed over the DNW in the first direction such that the DNW is disposed between the PSUB and the NWL in the first direction,
a first enhancement mode, N-type metal oxide semiconductor field effect transistor (first NMOS FET) formed in the semiconductor layer stack, the first NMOS FET including a first drain, a first source, and a first gate, the first drain being electrically coupled to the first power terminal, and the first source being electrically coupled to the switching terminal,
a second enhancement mode, N-type metal oxide semiconductor field effect transistor (second NMOS FET) formed in the semiconductor layer stack, the second NMOS FET including a second drain, a second source, and a second gate, the second drain being electrically coupled to the switching terminal, and the second source being electrically coupled to the second power terminal,
first driver circuitry formed in the semiconductor layer stack and configured to drive the first gate from a bootstrap power rail in response to a first control signal,
second driver circuitry formed in the semiconductor layer stack and configured to drive the second gate in response to a second control signal, and
bootstrap capacitance including one or more bootstrap trench capacitors formed in the semiconductor layer stack, each bootstrap trench capacitor being electrically coupled between the bootstrap power rail and the switching terminal and extending into the DNW and the NWL in the first direction,
wherein the DNW is electrically coupled to the bootstrap power rail and the PSUB is electrically coupled to the second power terminal.
8 . The integrated circuit of claim 7 , wherein a respective bottom plate terminal of each of the one or more bootstrap trench capacitors is electrically coupled to the bootstrap power rail.
9 . The integrated circuit of claim 7 , wherein a respective top plate terminal of each of the one or more bootstrap trench capacitors is electrically coupled to the switching terminal.
10 . The integrated circuit of claim 7 , wherein the semiconductor layer stack is formed according to a complementary metal oxide semiconductor (CMOS) fabrication process.
11 . A switching power converter, comprising:
an integrated circuit, the integrated circuit including:
an integrated circuit package including a first power terminal, a switching terminal, and a second power terminal, and
a semiconductor die housed in the integrated circuit package, the semiconductor die including:
a semiconductor layer stack including a P-type substrate (PSUB), a deep N-type well (DNW) formed over the PSUB in a first direction, and an N-type well (NWL) formed over the DNW in the first direction such that the DNW is disposed between the PSUB and the NWL in the first direction,
a first enhancement mode, N-type metal oxide semiconductor field effect transistor (first NMOS FET) formed in the semiconductor layer stack, the first NMOS FET including a first drain, a first source, and a first gate, the first drain being electrically coupled to the first power terminal, and the first source being electrically coupled to the switching terminal,
a second enhancement mode, N-type metal oxide semiconductor field effect transistor (second NMOS FET) formed in the semiconductor layer stack, the second NMOS FET including a second drain, a second source, and a second gate, the second drain being electrically coupled to the switching terminal, and the second source being electrically coupled to the second power terminal,
first driver circuitry formed in the semiconductor layer stack and configured to drive the first gate from a bootstrap power rail in response to a first control signal,
second driver circuitry formed in the semiconductor layer stack and configured to drive the second gate in response to a second control signal, and
bootstrap capacitance including one or more bootstrap trench capacitors formed in the semiconductor layer stack, each bootstrap trench capacitor being electrically coupled between the bootstrap power rail and the switching terminal, each bootstrap trench capacitor extending into each of the NWL and the DNW in the first direction,
wherein the DNW is electrically coupled to the bootstrap power rail and the PSUB is electrically coupled to the second power terminal; and
an inductor electrically coupled to the switching terminal.
12 . The switching power converter of claim 11 , wherein:
a respective bottom plate terminal of each of the one or more bootstrap trench capacitors is electrically coupled to the bootstrap power rail; and
a respective top plate terminal of each of the one or more bootstrap trench capacitors is electrically coupled to the switching terminal.
13 . The switching power converter of claim 11 , wherein the switching power converter is a buck converter.