IP Library › Granted Patent US 12,664,430
Granted Patent B1
US 12,664,430 · App. 18/651,516 · Granted Jun 23, 2026

Acceleration of neural networks with stacks of convolutional layers

Inventors: Thiam Khean Hah (San Jose, CA); Randy Renfu Huang (Morgan Hill, CA); Richard John Heaton (San Jose, CA); Ron Diamant (San Jose, CA); Vignesh Vivekraja (Santa Clara, CA)
Assignee: Amazon Technologies, Inc.
G06N3/08G06F13/20G06N3/04
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,664,430
App. No.
18/651,516
Granted
Jun 23, 2026
Kind
B1
Abstract

A neural network processor is configured to execute instructions in parallel on different computing engines (CEs) to perform convolution operations on an input dataset. The input dataset is divided into overlapping chunks, including a first chunk and a second chunk. Each CE processes a last portion of a respective chunk to compute respective shared states and receives additional shared states for processing. The first chunk is the respective chunk for a first CE. The second chunk is the respective chunk for a second CE. The additional shared states received by the second CE are the respective shared states computed by the first CE. The second CE receives the respective shared states computed by the first CE as a substitute for intermediate states that would otherwise have been computed by the second CE using a first portion of the second chunk.

Claims (60)

1 . A computer-implemented method comprising:

receiving a neural network model providing for an output dataset based on convolution operations; and

generating instructions for performing the convolution operations on a neural network processor and using an input dataset from an external memory, wherein the input dataset comprises a first chunk and a second chunk, and wherein the instructions are to be executed in parallel by a first computing engine (CE) and a second CE of the neural network processor to:

process a last portion of a respective chunk to compute respective shared states;

process a middle portion of the respective chunk to generate a first sub-portion of a respective portion of the output dataset;

receive, while processing the middle portion of the respective chunk, additional shared states for processing, wherein:

the first chunk is the respective chunk for the first CE,

the second chunk is the respective chunk for the second CE,

the last portion of the first chunk overlaps with a first portion of the second chunk,

the additional shared states received by the second CE are the respective shared states computed by the first CE and are obtained from a local memory of the first CE, and

the second CE receives the respective shared states computed by the first CE as a substitute for intermediate states that would otherwise have been computed by the second CE using the first portion of the second chunk; and

generate a second sub-portion of the respective portion of the output dataset using the received additional shared states.

2 . The computer-implemented method of claim 1 , wherein the instructions for performing the convolution operations comprise a same set of instructions for execution by the first CE and the second CE.

3 . The computer-implemented method of claim 1 , wherein the instructions for performing the convolution operations comprise an instruction for:

storing the respective shared states in a respective local memory while processing the last portion of the respective chunk.

4 . The computer-implemented method of claim 1 , wherein the instructions for performing the convolution operations comprise an instruction to provide the first CE with pre-computed states as the additional shared states.

5 . The computer-implemented method of claim 4 , wherein the pre-computed states have known or static values.

6 . The computer-implemented method of claim 4 , wherein:

the input dataset is a first input dataset in an input feature map, and

the respective shared states computed by the second CE are used as the pre-computed states for the first CE during processing of a second input dataset in the input feature map.

7 . The computer-implemented method of claim 1 , wherein the neural network model is a model of a dilated convolutional neural network (CNN), the dilated CNN comprising a first stack of dilated convolutional layers.

8 . The computer-implemented method of claim 7 , wherein the first chunk and the second chunk are inputs to a first layer in the first stack, and wherein the output dataset corresponds to outputs of a last layer in the first stack.

9 . The computer-implemented method of claim 8 , wherein the respective shared states correspond to outputs of the first layer and outputs of intervening layers between the first layer and the last layer.

10 . The computer-implemented method of claim 8 , wherein the dilated CNN further comprises a second stack of dilated convolutional layers, and wherein the outputs of the last layer in the first stack correspond to inputs of a first layer in the second stack.

11 . A neural network processor comprising:

a first computing engine (CE);

a second CE; and

an internal bus connecting the first CE and the second CE, wherein the neural network processor is configured to receive instructions for performing convolution operations using an input dataset from an external memory, wherein the input dataset comprises a first chunk and a second chunk, and wherein the instructions are to be executed in parallel by the first CE and the second CE to:

process a last portion of a respective chunk to compute respective shared states;

process a middle portion of the respective chunk to generate a first sub-portion of a respective portion of an output dataset;

receive, while processing the middle portion of the respective chunk, additional shared states for processing, wherein:

the first chunk is the respective chunk for the first CE,

the second chunk is the respective chunk for the second CE,

the last portion of the first chunk overlaps with a first portion of the second chunk,

the additional shared states received by the second CE are the respective shared states computed by the first CE and are obtained from a local memory of the first CE, and

the second CE receives the respective shared states computed by the first CE as a substitute for intermediate states that would otherwise have been computed by the second CE using the first portion of the second chunk; and

generate a second sub-portion of the respective portion of the output dataset using the received additional shared states.

12 . The neural network processor of claim 11 , wherein the instructions for performing the convolution operations comprise a same set of instructions for execution by the first CE and the second CE.

13 . The neural network processor of claim 11 , wherein the instructions for performing the convolution operations comprise an instruction for:

storing the respective shared states in a respective local memory while processing the last portion of the respective chunk.

14 . The neural network processor of claim 11 , wherein the instructions for performing the convolution operations comprise an instruction to provide the first CE with pre-computed states as the additional shared states.

15 . The neural network processor of claim 14 , wherein:

the input dataset is a first input dataset in an input feature map, and

the respective shared states computed by the second CE are used as the pre-computed states for the first CE during processing of a second input dataset in the input feature map.

16 . The neural network processor of claim 11 , wherein the instructions for performing the convolution operations implement a model of a dilated convolutional neural network (CNN), the dilated CNN comprising a first stack of dilated convolutional layers.

17 . The neural network processor of claim 16 , wherein the first chunk and the second chunk are inputs to a first layer in the first stack, and wherein the output dataset corresponds to outputs of a last layer in the first stack.

18 . The neural network processor of claim 17 , wherein the respective shared states correspond to outputs of the first layer and outputs of intervening layers between the first layer and the last layer.

19 . The neural network processor of claim 17 , wherein the dilated CNN further comprises a second stack of dilated convolutional layers, and wherein the outputs of the last layer in the first stack correspond to inputs of a first layer in the second stack.

20 . A non-transitory computer readable medium having stored therein instructions that, when executed by one or more processors, cause the one or more processors to execute a compiler, the compiler performing operations including:

receiving a neural network model providing for an output dataset based on convolution operations; and

generating instructions for performing the convolution operations on a neural network processor and using an input dataset from an external memory, wherein the input dataset comprises a first chunk and a second chunk, and wherein the instructions are to be executed in parallel by a first computing engine (CE) and a second CE of the neural network processor to:

process a last portion of a respective chunk to compute respective shared states;

process a middle portion of the respective chunk to generate a first sub-portion of a respective portion of the output dataset;

receive, while processing the middle portion of the respective chunk, additional shared states for processing, wherein:

the first chunk is the respective chunk for the first CE,

the second chunk is the respective chunk for the second CE,

the last portion of the first chunk overlaps with a first portion of the second chunk,

the additional shared states received by the second CE are the respective shared states computed by the first CE and are obtained from a local memory of the first CE, and

the second CE receives the respective shared states computed by the first CE as a substitute for intermediate states that would otherwise have been computed by the second CE using the first portion of the second chunk; and

generate a second sub-portion of the respective portion of the output dataset using the received additional shared states.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 1, 2024
From: HAH, THIAM KHEAN; HUANG, RANDY RENFU; HEATON, RICHARD JOHN; DIAMANT, RON; VIVEKRAJA, VIGNESH
To: AMAZON TECHNOLOGIES, INC.
Reel/Frame 067287/0405 →
Continuity (1)
Continuation 17009517 · Sep 1, 2020
References Cited (34)
US 10878316B2 · Ross · 2020 [cited by applicant]
US 10984290B1 · Goel et al. · 2021 [cited by applicant]
US 11875247B1 · Heaton et al. · 2024 [cited by applicant]
US 12008469B1 · Hah et al. · 2024 [cited by applicant]
US 20180075343A1 · van den Oord · 2018 [cited by examiner]
US 20180307980A1 · Barik et al. · 2018 [cited by applicant]
US 20190012295A1 · Yinger et al. · 2019 [cited by applicant]
US 20190114547A1 · Jaganathan et al. · 2019 [cited by applicant]
US 20190130269A1 · Nicol · 2019 [cited by examiner]
US 20190340508A1 · Liu et al. · 2019 [cited by applicant]
US 20190370645A1 · Lee et al. · 2019 [cited by applicant]
US 20190377965A1 · Totolos, Jr. et al. · 2019 [cited by applicant]
US 20200175313A1 · Jang · 2020 [cited by applicant]
US 20200302297A1 · Jaganathan et al. · 2020 [cited by applicant]
US 20210192328A1 · Ross · 2021 [cited by applicant]
US 20230273829A1 · Xu et al. · 2023 [cited by applicant]
CN 111563586A · 2020 [cited by examiner]
U.S. Notice of Allowance dated Sep. 11, 2024 in U.S. Appl. No. 17/009,483. [cited by applicant]
Claessens, B., et al., “Convolutional Neural Networks for Automatic State-Time Feature Extraction in Reinforcement Learning Applied to Residential Load Control,” IEEE Transactions on Smart Grid, Jul. 2018, vol. 9, No. 4… [cited by applicant]
Elman, J. L., “Finding Structure in Time,” Cognitive Science 14, 1990, pp. 179-211. [cited by applicant]
Huang, C., et al, “eCNN: A Block-Based and Highly-Parallel CN-N Accelerator for Edge Inference,” MICRO '52: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, Oct. 2019, pp. 182-195. [cited by applicant]
Im, D., et al., “DT-CNN: Dilated and Transposed Convolution Neural Network Accelerator for Real-time Image Segmentation on Mobile Devices,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, pp. 1-… [cited by applicant]
Lee, S., et al., “Parallel Deep Convolutional Neural Network Training by Exploiting the Overlapping of Computation and Communication,” 2017 IEEE 24th International Conference on High Performance Computing (HiPC), 2017, … [cited by applicant]
Lin, G., et al., “Image super-resolution using a dilated convolutional neural network,” Neurocomputing, Jan. 31, 2018, vol. 275, pp. 1219-1230. [cited by applicant]
Machine translation of CN Appl. Pub. No. CN111563586A (Aug. 21, 2020), Specification only, 20 pages. [cited by applicant]
Pooja, K., et al., “Multi-Scale Dilated Residual Convolutional Neural Network for Hyperspectral Image Classification,” 2019 10th Workshop on Hyperspectral Imaging and Signal Processing: Evolution in Remote Sensing (WHIS… [cited by applicant]
U.S. Final Office Action dated Oct. 2, 2023 in U.S. Appl. No. 17/009,517. [cited by applicant]
U.S. Final Office Action dated Oct. 19, 2023 in U.S. Appl. No. 17/009,483. [cited by applicant]
U.S. Non-Final Office Action dated Apr. 17, 2023 in U.S. Appl. No. 17/009,517. [cited by applicant]
U.S. Non-Final Office Action dated Jun. 9, 2023 in U.S. Appl. No. 17/009,483. [cited by applicant]
U.S. Non-Final Office Action dated May 2, 2024 in U.S. Appl. No. 17/009,483. [cited by applicant]
U.S. Notice of Allowance dated Feb. 2, 2024 in U.S. Appl. No. 17/009,517. [cited by applicant]
U.S. Appl. No. 17/009,483, “Accelerated Convolution of Neural Networks,” filed Sep. 1, 2020. [cited by applicant]
Zhang, X., et al., “Dilated Convolution Neural Network with LeakyReLU for Environmental Sound Classification,” 2017 22nd International Conference on Digital Signal Processing (DSP), 2017, pp. 1-5. [cited by applicant]