Configurable-aggregation retimer with lane-dedicated controllers
Groups of signal conductors within a configurable communication system are managed by respective, dedicated media controllers implement a configurable number of independent communication channels through coordinated action so that signal conductors need not be multiplexed to/from multiple controllers and no media controllers or input/output driver circuits therein need be disabled in any configuration.
1 . An integrated circuit component comprising:
a first signaling interface to be coupled to a plurality of signaling lanes;
lane controllers dedicated to controlling communication via respective subsets of the signaling lanes, each of the lane controllers having:
circuitry to monitor a respective stream of information received via the respective subset of the signaling lanes for predetermined control information,
output circuitry to transmit an event-detect signal in response to detecting the predetermined control information, and
input circuitry to receive event-detect signals transmitted by the output circuitry of each of the others of the lane controllers; and
a synchronization bus that interconnects the output circuitry of each of the lane controllers to the input circuitry of each of the others of the lane controllers such that an event-detect signal transmitted by the output circuitry within any one of the lane controllers is received via the respective input circuitry within each of the others of the lane controllers.
2 . The integrated circuit component of claim 1 wherein each of the lane controllers further comprises circuitry to detect assertion of a first control signal, and wherein the circuitry within each of the lane controllers to monitor the respective stream of information comprises circuitry to commence monitoring the respective stream of information in response to assertion of the first control signal such that all lane controllers concurrently monitor the respective streams of information.
3 . The integrated circuit component of claim 1 wherein the respective streams of information received via the respective subsets of signaling lanes comprises respective streams of symbols organized in blocks, and wherein the predetermined control information comprises a block of symbols identifiable, by each of the lane controllers, as a temporal marker.
4 . The integrated circuit component of claim 3 wherein the respective streams of symbols are protocol-compliant with a Peripheral Component Interconnect Express (PCIe) specification, and wherein the block of symbols identifiable, by each of the lane controllers, as a temporal marker comprises a PCIe skip ordered set (SKPOS).
5 . The integrated circuit component of claim 1 further comprising a second signaling interface to which the lane controllers forward the respective streams of information for output from the integrated circuit component.
6 . The integrated circuit component of claim 5 further comprising alignment circuitry within each of the lane controllers and that, for each one of the lane controllers for which the predetermined control information is detected prior to receiving respective event-detect signals from all others of the lane controllers, ceases forwarding the respective stream of information to the second interface throughout a respective alignment time interval that commences at detection of the predetermined control information within the one of the lane controllers and concludes after respective event-detect signals have been received from all others of the lane controllers.
7 . The integrated circuit component of claim 6 wherein the alignment circuitry comprises circuitry that, for each one of the lane controllers for which the predetermined control information is detected prior to receiving respective event-detect signals from all others of the lane controllers, reverts to forwarding the respective stream of information to the second interface at conclusion of the respective alignment time interval.
8 . The integrated circuit component of claim 7 wherein the alignment circuitry within the lane controller for the respective stream of information within which the predetermined control information is detected later in time than for all others of the respective streams of information comprises circuitry to forward that stream of information to the second interface without cessation following detection of the predetermined control information therein.
9 . The integrated circuit component of claim 8 wherein the alignment circuitry comprises circuitry that, for each one of the lane controllers for which the predetermined control information is detected prior to receiving respective event-detect signals from all others of the lane controllers, reverts to forwarding the respective stream of information to the second interface in response to receiving the event-detect signal output from the lane controller dedicated to controlling communication via the respective subset of the signaling lanes conveying the stream of information within which the predetermined control information is detected later in time than for all others of the respective streams of information.
10 . The integrated circuit component of claim 5 further comprising configuration circuitry to store information that defines two or more subsets of the lane controllers, and wherein each one of the lane controllers for which the predetermined control information is detected prior to receiving respective event-detect signals from all others of the lane controllers within the same subset of the lane controllers, ceases forwarding the respective stream of information to the second interface throughout a respective alignment time interval that commences at detection of the predetermined control information within the one of the lane controllers and concludes after respective event-detect signals have been received from all others of the lane controllers within the same subset of the lane controllers.
11 . The integrated circuit component of claim 1 wherein the lane controllers comprise respective registers to store respective link aggregation values that indicate one or more quantities of the subsets of the signaling lanes aggregated to form a signaling link for which communication is controlled by either (i) all the lane controllers or (ii) a subset of the lane controllers, fewer than all.
12 . A method of operation within an integrated circuit component having a first signaling interface coupled to a plurality of signaling lanes, lane controllers dedicated to controlling communication via respective subsets of the signaling lanes, and a synchronization bus that couples each of the lane controllers to each of the others of the lane controllers, the method comprising:
concurrently monitoring, within all the lane controllers, respective streams of information received via the respective subsets of the signaling lanes for predetermined control information;
outputting, from each of the lane controllers via the synchronization bus, a respective event-detect signal in response to detecting the predetermined control information within the stream of information received via the respective subset of the signaling lanes;
receiving, within each of the lane controllers via the synchronization bus, respective event-detect signals output by all others of the lane controllers.
13 . The method of claim 12 further comprising detecting, within each of the lane controllers, assertion of a first control signal, and wherein concurrently monitoring, within all the lane controllers, the information propagating via the respective subsets of signaling lanes comprises commencing, within each of the lane controllers, monitoring information propagating via the respective subset of signaling lanes in response to assertion of the first control signal.
14 . The method of claim 12 wherein the respective streams of information received via the respective subsets of signaling lanes comprises respective streams of symbols organized in blocks, and wherein the predetermined control information comprises a block of symbols identifiable, by each of the lane controllers, as a temporal marker.
15 . The method of claim 14 wherein the respective streams of symbols are protocol-compliant with a Peripheral Component Interconnect Express (PCIe) specification, and wherein the block of symbols identifiable, by each of the lane controllers, as a temporal marker comprises a PCIe skip ordered set (SKPOS).
16 . The method of claim 12 further comprising forwarding the respective streams of information from the lane controllers to a second signaling interface for output from the integrated circuit component.
17 . The method of claim 16 further comprising, within each one of the lane controllers for which the predetermined control information is detected prior to receiving respective event-detect signals from all others of the lane controllers, ceasing forwarding the respective stream of information to the second interface throughout a respective alignment time interval that commences at detection of the predetermined control information within the one of the lane controllers and concludes after respective event-detect signals have been received from all others of the lane controllers.
18 . The method of claim 17 further comprising, within each one of the lane controllers for which the predetermined control information is detected prior to receiving respective event-detect signals from all others of the lane controllers, reverting to forwarding the respective stream of information to the second interface at conclusion of the respective alignment time interval.
19 . The method of claim 18 further comprising forwarding to the second interface without cessation the respective stream of information within which the predetermined control information is detected later in time than for all others of the respective streams of information.
20 . The method of claim 19 wherein each one of the lane controllers for which the predetermined control information is detected prior to receiving respective event-detect signals from all others of the lane controllers reverts to forwarding the respective stream of information to the second interface in response to receiving the event-detect signal output from the lane controller dedicated to controlling communication via the respective subset of the signaling lanes conveying the stream of information within which the predetermined control information is detected later in time than for all others of the respective streams of information.
21 . The method of claim 16 further comprising storing information that defines two or more subsets of the lane controllers, and wherein each one of the lane controllers for which the predetermined control information is detected prior to receiving respective event-detect signals from all others of the lane controllers within the same subset of the lane controllers, ceases forwarding the respective stream of information to the second interface throughout a respective alignment time interval that commences at detection of the predetermined control information within the one of the lane controllers and concludes after respective event-detect signals have been received from all others of the lane controllers within the same subset of the lane controllers.
22 . The method of claim 12 further comprising storing, within registers corresponding respectively to the lane controllers, respective link aggregation values that indicate one or more quantities of the subsets of the signaling lanes aggregated to form a signaling link for which communication is controlled by either (i) all the lane controllers or (ii) a subset of the lane controllers, fewer than all.
23 . An integrated circuit component comprising:
a first signaling interface to be coupled to a plurality of signaling lanes;
lane controllers dedicated to controlling communication via respective subsets of the signaling lanes, each of the lane controllers having:
means for monitoring a respective stream of information received via the respective subset of the signaling lanes for predetermined control information
means for transmitting an event-detect signal in response to detecting the predetermined control information, and
means for receiving event-detect signals transmitted by the means for transmitting within each of the others of the lane controllers; and
means for interconnecting the means for transmitting within each of the lane controllers to the means for receiving within each of the others of the lane controllers such that an event-detect signal transmitted by the means for transmitting within any one of the lane controllers is received via the respective means for receiving within each of the others of the lane controllers.